[PW_SID:1059453] [v5,1/8] iommu/riscv: Enable IOMMU DMA mapping support#1523
[PW_SID:1059453] [v5,1/8] iommu/riscv: Enable IOMMU DMA mapping support#1523linux-riscv-bot wants to merge 8 commits into
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Enable IOMMU DMA mapping support for RISC-V, so that DMACs can be tested with translation enabled. Known Possible Issue: 1. When CONFIG_IOMMU_DMA is enabled, on the tested Linux, RISC-V IOMMU is lack of PCIe support, causing riscv_iommu_fault:522 in dealing with NVMe PCIe devices. Signed-off-by: Jingyu Li <joey.li@spacemit.com> Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Introduces auxiliary bus support for RISC-V IOMMU to enable modular
extension of IOMMU capabilities. The framework allows creating auxiliary
devices that can be bound to separate drivers.
The IOMMU HPM featured PMU device ("iommu.riscv_iommu_hpm.0") is created
and registered as RISC-V IOMMU auxiliary device.
Signed-off-by: Jingyu Li <joey.li@spacemit.com>
Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com>
Link: https://github.com/riscv-non-isa/riscv-iommu
Cc: Zong Li <zong.li@sifive.com>
Cc: Yaxing Guo <guoyaxing@bosc.ac.cn>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Introduces perf-based HPM driver for RISC-V IOMMU, enabling performance monitoring capabilities. Note that the RISC-V IOMMU HPM module uses COUNTER_MAX-1 as a static counter index of HPMCYCLES, and 0~COUNTER_MAX-2 as the dynamic counter indexes of other HPMEVENTS in order to correctly index into IOHPMEVT and IOHPMCTR registers that have already been defined in the iommu-bits.h. However the users treat 0 as the index of HPMCYCLES and 1~COUNTER_MAX-1 as the indexes of other HPMEVENTS, thus care should be taken in dealing with counter indexes between userspace and kernel space. Signed-off-by: Jingyu Li <joey.li@spacemit.com> Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com> Link: https://github.com/riscv-non-isa/riscv-iommu Cc: Zong Li <zong.li@sifive.com> Cc: Yaxing Guo <guoyaxing@bosc.ac.cn> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Adds device tree bindings for SpacemiT T100 specific features by introducing spacemit,t100 compatible. T100 contains distributed IOATCs, each of which exposes pmiv interrupt. Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com> Signed-off-by: Jingyu Li <joey.li@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Adds global filter support for RISC-V IOMMU HPM. The global filter can be seen in SpacemiT T100 which only supports single filter to be applied to all event counters. Drivers can program filters in each iohpmevt registers as normal in such a silicon design, however the underlying hardware filters are wired together as a global filter applying to all iohpmevt(s). Since the mechanism is compatible with standard iohpmevt in programming interface, only adds sanity checks to allow it to be configured with "global" awareness to inform users a filter incompatiblity. Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com> Signed-off-by: Jingyu Li <joey.li@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add IOATC discovery and HPM support for SpacemiT T100. SpacemiT T100 supports distributed architecture which allows IOTLBs to be cached in adjacent to the DMA masters. Such IOTLB controllers are called as IOATCs. Adds distributed HPM support for IOATCs. Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com> Signed-off-by: Jingyu Li <joey.li@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add a mechanism to allow vendor events to be registered via userspace jevents. The PMU exposes an "identifier" sysfs attribute derived from the device tree compatible string (e.g. "spacemit,t100" or "riscv,iommu"), which perf's jevents uses to match JSON event definitions to the PMU. Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com> Signed-off-by: Jingyu Li <joey.li@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add JSON HPM event aliases for SpacemiT distributed IOMMU (T100) which is general and compatible for all SpacemiT RISC-V SoCs. Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com> Signed-off-by: Jingyu Li <joey.li@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v5,1/8] iommu/riscv: Enable IOMMU DMA mapping support" |
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Patch 1: "[v5,1/8] iommu/riscv: Enable IOMMU DMA mapping support" |
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Patch 1: "[v5,1/8] iommu/riscv: Enable IOMMU DMA mapping support" |
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Patch 1: "[v5,1/8] iommu/riscv: Enable IOMMU DMA mapping support" |
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Patch 1: "[v5,1/8] iommu/riscv: Enable IOMMU DMA mapping support" |
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Patch 1: "[v5,1/8] iommu/riscv: Enable IOMMU DMA mapping support" |
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Patch 1: "[v5,1/8] iommu/riscv: Enable IOMMU DMA mapping support" |
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Patch 1: "[v5,1/8] iommu/riscv: Enable IOMMU DMA mapping support" |
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Patch 1: "[v5,1/8] iommu/riscv: Enable IOMMU DMA mapping support" |
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Patch 1: "[v5,1/8] iommu/riscv: Enable IOMMU DMA mapping support" |
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Patch 1: "[v5,1/8] iommu/riscv: Enable IOMMU DMA mapping support" |
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Patch 1: "[v5,1/8] iommu/riscv: Enable IOMMU DMA mapping support" |
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Patch 2: "[v5,2/8] iommu/riscv: Add auxiliary bus framework and HPM device support" |
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Patch 2: "[v5,2/8] iommu/riscv: Add auxiliary bus framework and HPM device support" |
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Patch 2: "[v5,2/8] iommu/riscv: Add auxiliary bus framework and HPM device support" |
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Patch 2: "[v5,2/8] iommu/riscv: Add auxiliary bus framework and HPM device support" |
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Patch 2: "[v5,2/8] iommu/riscv: Add auxiliary bus framework and HPM device support" |
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Patch 2: "[v5,2/8] iommu/riscv: Add auxiliary bus framework and HPM device support" |
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Patch 2: "[v5,2/8] iommu/riscv: Add auxiliary bus framework and HPM device support" |
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Patch 2: "[v5,2/8] iommu/riscv: Add auxiliary bus framework and HPM device support" |
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Patch 2: "[v5,2/8] iommu/riscv: Add auxiliary bus framework and HPM device support" |
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Patch 2: "[v5,2/8] iommu/riscv: Add auxiliary bus framework and HPM device support" |
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Patch 6: "[v5,6/8] iommu/riscv: Add SpacemiT T100 IOATC HPM support" |
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Patch 6: "[v5,6/8] iommu/riscv: Add SpacemiT T100 IOATC HPM support" |
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Patch 6: "[v5,6/8] iommu/riscv: Add SpacemiT T100 IOATC HPM support" |
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Patch 6: "[v5,6/8] iommu/riscv: Add SpacemiT T100 IOATC HPM support" |
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Patch 7: "[v5,7/8] iommu/riscv: Add vendor event support for RISC-V IOMMU HPM" |
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Patch 7: "[v5,7/8] iommu/riscv: Add vendor event support for RISC-V IOMMU HPM" |
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Patch 7: "[v5,7/8] iommu/riscv: Add vendor event support for RISC-V IOMMU HPM" |
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Patch 7: "[v5,7/8] iommu/riscv: Add vendor event support for RISC-V IOMMU HPM" |
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Patch 7: "[v5,7/8] iommu/riscv: Add vendor event support for RISC-V IOMMU HPM" |
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Patch 7: "[v5,7/8] iommu/riscv: Add vendor event support for RISC-V IOMMU HPM" |
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Patch 7: "[v5,7/8] iommu/riscv: Add vendor event support for RISC-V IOMMU HPM" |
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Patch 7: "[v5,7/8] iommu/riscv: Add vendor event support for RISC-V IOMMU HPM" |
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Patch 7: "[v5,7/8] iommu/riscv: Add vendor event support for RISC-V IOMMU HPM" |
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Patch 7: "[v5,7/8] iommu/riscv: Add vendor event support for RISC-V IOMMU HPM" |
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Patch 7: "[v5,7/8] iommu/riscv: Add vendor event support for RISC-V IOMMU HPM" |
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Patch 7: "[v5,7/8] iommu/riscv: Add vendor event support for RISC-V IOMMU HPM" |
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Patch 8: "[v5,8/8] perf vendor events riscv: Add SpacemiT T100 HPM event aliases" |
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Patch 8: "[v5,8/8] perf vendor events riscv: Add SpacemiT T100 HPM event aliases" |
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Patch 8: "[v5,8/8] perf vendor events riscv: Add SpacemiT T100 HPM event aliases" |
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Patch 8: "[v5,8/8] perf vendor events riscv: Add SpacemiT T100 HPM event aliases" |
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Patch 8: "[v5,8/8] perf vendor events riscv: Add SpacemiT T100 HPM event aliases" |
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Patch 8: "[v5,8/8] perf vendor events riscv: Add SpacemiT T100 HPM event aliases" |
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Patch 8: "[v5,8/8] perf vendor events riscv: Add SpacemiT T100 HPM event aliases" |
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Patch 8: "[v5,8/8] perf vendor events riscv: Add SpacemiT T100 HPM event aliases" |
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Patch 8: "[v5,8/8] perf vendor events riscv: Add SpacemiT T100 HPM event aliases" |
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Patch 8: "[v5,8/8] perf vendor events riscv: Add SpacemiT T100 HPM event aliases" |
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Patch 8: "[v5,8/8] perf vendor events riscv: Add SpacemiT T100 HPM event aliases" |
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Patch 8: "[v5,8/8] perf vendor events riscv: Add SpacemiT T100 HPM event aliases" |
PR for series 1059453 applied to workflow__riscv__fixes
Name: [v5,1/8] iommu/riscv: Enable IOMMU DMA mapping support
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1059453
Version: 5