[PW_SID:1064195] clk: sunxi-ng: Add support for Allwinner A733 CCU and PRCM#1586
[PW_SID:1064195] clk: sunxi-ng: Add support for Allwinner A733 CCU and PRCM#1586linux-riscv-bot wants to merge 8 commits into
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The CCU and R-CCU (PRCM) modules provide clocks and reset functions for the Allwinner A733 SoC. The clock architecture of the A733 is evolved from the A523, though the root clocking strategy transitions from a static oscillator frequency in the Devicetree to the "hosc" clock, which is determined by choosing from three possible frequencies (19.2MHz, 24MHz, or 26MHz) by the RTC hardware, and finally feeds the CCU and R-CCU. Additionally, the MCU_CCU module found in previous designs is removed from the A733, and the clock tree is expanded with more clock outputs to support new functional modules. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
On newer Allwinner platforms like the A733, the Sigma-Delta Modulation (SDM) control logic is more complex. The SDM enable bit, which was previously located in the PLL register, is now moved to a second pattern register (PATTERN1). To support this, rename the existing "tuning" members to "pattern0" to align with the datasheet, and introduce the _SUNXI_CCU_SDM_DUAL_PAT macro to provide pattern1 register support. Related operations are also updated. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add support for the Power Reset Clock Management (PRCM) module found in the Allwinner A733 SoC. This clock controller manages the clock control and reset functions for device modules within the CPUS domain. The PRCM module includes the management of three primary buses: r-ahb, r-apb0, and r-apb1. It also provides clocking for several key peripherals, such as R-UART, R-I2C, R-SPI, and the R-RISCV subsystem. Additionally, the reset lines for these modules are integrated. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add PLL clock support for the main CCU of the Allwinner A733 SoC. The structure is mostly similar to the sun55i, with the addition of a PLL_REF clock that normalizes the hardware-detected DCXO/hosc frequency (19.2MHz, 24MHz, or 26MHz) into a consistent 24MHz reference for all subsequent PLLs. The behaviors of PLL_AUDIO0 and PLL_AUDIO1 are ported from the vendor driver. Specifically, PLL_AUDIO0 is configured with SDM parameters to provide a 22.5792MHz * 4 output, while PLL_AUDIO1 is integrated into the main CCU without using SDM. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add the essential bus clocks in the Allwinner A733 CCU, including AHB, APB0, APB1, APB_UART, NSI, and MBUS. These buses are necessary for many other functional modules. Additionally clocks such as trace, gic and cpu_peri are also added as they fall within the register address range of the bus clocks, even though they are not strictly bus clocks. The MBUS clock is marked as critical to ensure the memory bus remains operational at all times. For the NSI and MBUS clocks, the hardware requires an update bit (bit 27) to be set so that the configuration takes effect and the updated parameters can be correctly read back. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add the module clocks found in the Allwinner A733 SoC, including video, storage, interfaces and others. While most of these clocks are similar to those in the A523 SoC, this implementation accounts for changes in register offsets and introduces support for new modules. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add the bus clock gates that control access to the devices' register interface on the Allwinner A733 SoC. These clocks are typically single-bit controls in the BGR registers, covering UARTs, SPI, I2C, and various multimedia engines. It also includes bus gates for system components like the IOMMU and MSI-lite interfaces. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add the reset lines for the Allwinner A733 SoC. These reset control bits are integrated into the Bus Gate Reset (BGR) registers, typically sharing the same register address with their corresponding bus clock gates. Integrate them into the main CCU driver using the existing sunxi-ng ccu_reset framework, allowing the CCU to also function as a reset controller for the SoC. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[RFC,1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support" |
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Patch 1: "[RFC,1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support" |
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Patch 1: "[RFC,1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support" |
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Patch 1: "[RFC,1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support" |
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Patch 1: "[RFC,1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support" |
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Patch 1: "[RFC,1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support" |
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Patch 1: "[RFC,1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support" |
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Patch 1: "[RFC,1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support" |
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Patch 1: "[RFC,1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support" |
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Patch 1: "[RFC,1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support" |
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Patch 1: "[RFC,1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support" |
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Patch 1: "[RFC,1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support" |
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Patch 2: "[RFC,2/8] clk: sunxi-ng: sdm: Add dual patterns support" |
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Patch 2: "[RFC,2/8] clk: sunxi-ng: sdm: Add dual patterns support" |
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Patch 2: "[RFC,2/8] clk: sunxi-ng: sdm: Add dual patterns support" |
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Patch 2: "[RFC,2/8] clk: sunxi-ng: sdm: Add dual patterns support" |
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Patch 2: "[RFC,2/8] clk: sunxi-ng: sdm: Add dual patterns support" |
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Patch 2: "[RFC,2/8] clk: sunxi-ng: sdm: Add dual patterns support" |
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Patch 2: "[RFC,2/8] clk: sunxi-ng: sdm: Add dual patterns support" |
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Patch 2: "[RFC,2/8] clk: sunxi-ng: sdm: Add dual patterns support" |
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Patch 2: "[RFC,2/8] clk: sunxi-ng: sdm: Add dual patterns support" |
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Patch 2: "[RFC,2/8] clk: sunxi-ng: sdm: Add dual patterns support" |
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Patch 6: "[RFC,6/8] clk: sunxi-ng: a733: Add mod clocks support" |
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Patch 6: "[RFC,6/8] clk: sunxi-ng: a733: Add mod clocks support" |
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Patch 6: "[RFC,6/8] clk: sunxi-ng: a733: Add mod clocks support" |
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Patch 6: "[RFC,6/8] clk: sunxi-ng: a733: Add mod clocks support" |
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Patch 7: "[RFC,7/8] clk: sunxi-ng: a733: Add bus clock gates" |
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Patch 7: "[RFC,7/8] clk: sunxi-ng: a733: Add bus clock gates" |
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Patch 7: "[RFC,7/8] clk: sunxi-ng: a733: Add bus clock gates" |
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Patch 7: "[RFC,7/8] clk: sunxi-ng: a733: Add bus clock gates" |
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Patch 7: "[RFC,7/8] clk: sunxi-ng: a733: Add bus clock gates" |
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Patch 7: "[RFC,7/8] clk: sunxi-ng: a733: Add bus clock gates" |
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Patch 7: "[RFC,7/8] clk: sunxi-ng: a733: Add bus clock gates" |
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Patch 7: "[RFC,7/8] clk: sunxi-ng: a733: Add bus clock gates" |
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Patch 7: "[RFC,7/8] clk: sunxi-ng: a733: Add bus clock gates" |
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Patch 7: "[RFC,7/8] clk: sunxi-ng: a733: Add bus clock gates" |
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Patch 7: "[RFC,7/8] clk: sunxi-ng: a733: Add bus clock gates" |
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Patch 7: "[RFC,7/8] clk: sunxi-ng: a733: Add bus clock gates" |
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Patch 8: "[RFC,8/8] clk: sunxi-ng: a733: Add reset lines" |
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Patch 8: "[RFC,8/8] clk: sunxi-ng: a733: Add reset lines" |
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Patch 8: "[RFC,8/8] clk: sunxi-ng: a733: Add reset lines" |
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Patch 8: "[RFC,8/8] clk: sunxi-ng: a733: Add reset lines" |
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Patch 8: "[RFC,8/8] clk: sunxi-ng: a733: Add reset lines" |
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Patch 8: "[RFC,8/8] clk: sunxi-ng: a733: Add reset lines" |
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Patch 8: "[RFC,8/8] clk: sunxi-ng: a733: Add reset lines" |
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Patch 8: "[RFC,8/8] clk: sunxi-ng: a733: Add reset lines" |
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Patch 8: "[RFC,8/8] clk: sunxi-ng: a733: Add reset lines" |
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Patch 8: "[RFC,8/8] clk: sunxi-ng: a733: Add reset lines" |
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Patch 8: "[RFC,8/8] clk: sunxi-ng: a733: Add reset lines" |
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Patch 8: "[RFC,8/8] clk: sunxi-ng: a733: Add reset lines" |
PR for series 1064195 applied to workflow__riscv__fixes
Name: clk: sunxi-ng: Add support for Allwinner A733 CCU and PRCM
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1064195
Version: 1