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[PW_SID:1072898] RISC-V: restore U-mode counter access (scounteren) #1672

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[PW_SID:1072898] RISC-V: restore U-mode counter access (scounteren) #1672

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8 changes: 4 additions & 4 deletions arch/riscv/kernel/head.S
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Original file line number Diff line number Diff line change
Expand Up @@ -133,8 +133,8 @@ secondary_start_sbi:
csrw CSR_IP, zero

#ifndef CONFIG_RISCV_M_MODE
/* Enable time CSR */
li t0, 0x2
/* Enable CY, TM, and IR counters in U mode */
li t0, 0x7
csrw CSR_SCOUNTEREN, t0
#endif

Expand Down Expand Up @@ -247,8 +247,8 @@ SYM_CODE_START(_start_kernel)
*/
csrr a0, CSR_MHARTID
#else
/* Enable time CSR */
li t0, 0x2
/* Enable CY, TM, and IR counters in U mode */
li t0, 0x7
csrw CSR_SCOUNTEREN, t0
#endif /* CONFIG_RISCV_M_MODE */

Expand Down