[PW_SID:1074514] refactor Andes cache driver for generic platform support#1690
[PW_SID:1074514] refactor Andes cache driver for generic platform support#1690linux-riscv-bot wants to merge 22 commits into
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Fix various typos in RISC-V architecture code and comments. The following changes are included: - arch/riscv/errata/thead/errata.c: "futher" → "further" - arch/riscv/include/asm/atomic.h: "therefor" → "therefore", "arithmatic" → "arithmetic" - arch/riscv/include/asm/elf.h: "availiable" → "available", "coorespends" → "corresponds" - arch/riscv/include/asm/processor.h: "requries" → "is required" - arch/riscv/include/asm/thread_info.h: "returing" → "returning" - arch/riscv/kernel/acpi.c: "compliancy" → "compliance" - arch/riscv/kernel/ftrace.c: "therefor" → "therefore" - arch/riscv/kernel/head.S: "intruction" → "instruction" - arch/riscv/kernel/mcount-dyn.S: "localtion → "location" - arch/riscv/kernel/module-sections.c: "maxinum" → "maximum" - arch/riscv/kernel/probes/kprobes.c: "reenabled" → "re-enabled" - arch/riscv/kernel/probes/uprobes.c: "probbed" → "probed" - arch/riscv/kernel/soc.c: "extremly" → "extremely" - arch/riscv/kernel/suspend.c: "incosistent" → "inconsistent" - arch/riscv/kvm/tlb.c: "cahce" → "cache" - arch/riscv/kvm/vcpu_pmu.c: "indicies" → "indices" - arch/riscv/lib/csum.c: "implmentations" → "implementations" - arch/riscv/lib/memmove.S: "ammount" → "amount" - arch/riscv/mm/cacheflush.c: "visable" → "visible" - arch/riscv/mm/physaddr.c: "aginst" → "against" Signed-off-by: Sean Chang <seanwascoding@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260212163325.60389-1-seanwascoding@gmail.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
Commit f1a0a37 ("sched/core: Initialize the idle task with preemption disabled") removed a call to preempt_disable(), but not the associated comment. Remove the outdated comment. Fixes: f1a0a37 ("sched/core: Initialize the idle task with preemption disabled") Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn> Link: https://patch.msgid.link/20260204-riscv-smp-comment-update-2026-01-v1-1-8b77aa181530@iscas.ac.cn Signed-off-by: Paul Walmsley <pjw@kernel.org>
local_flush_icache_all() only flushes and synchronizes the *instruction* cache, not the data cache. Since RISC-V does have a cbo.flush instruction for data cache flush, clarify the comment to avoid confusion. Fixes: 58661a3 ("riscv: Flush the instruction cache during SMP bringup") Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn> Link: https://patch.msgid.link/20260204-riscv-smp-comment-update-2026-01-v1-2-8b77aa181530@iscas.ac.cn Signed-off-by: Paul Walmsley <pjw@kernel.org>
The kaslr_offset() function is a simple accessor that returns kernel_map.virt_offset. This commit change also ensures that kaslr_offset() is consistently available across various kernel configurations without requiring explicit linkage to mm/init.c. Signed-off-by: Austin Kim <austin.kim@lge.com> Link: https://patch.msgid.link/aYwJ76yHaMbbQVJA@adminpc-PowerEdge-R7525 Signed-off-by: Paul Walmsley <pjw@kernel.org>
The following options are required by the kdump crash utility for RISC-V
based vmcore file:
- kaslr: If the vmcore is generated from a KASLR-enabled Linux kernel,
the KASLR offset is required for the crash utility to load
the vmcore. Without the proper kaslr option, the crash utility
fails to load the vmcore file.
- satp: The exact root page table address helps determine the correct base
PGD address.
With this patch, RISC-V VMCOREINFO ELF notes now include both kaslr
and satp information.
Signed-off-by: Austin Kim <austin.kim@lge.com>
Link: https://patch.msgid.link/aYwKUE3ZzN7/ZY/A@adminpc-PowerEdge-R7525
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Fix several bugs in the RISC-V kgdb implementation: - The element of dbg_reg_def[] that is supposed to pertain to the S1 register embeds instead the struct pt_regs offset of the A1 register. Fix this to use the S1 register offset in struct pt_regs. - The sleeping_thread_to_gdb_regs() function copies the value of the S10 register into the gdb_regs[] array element meant for the S9 register, and copies the value of the S11 register into the array element meant for the S10 register. It also neglects to copy the value of the S11 register. Fix all of these issues. Fixes: fe89bd2 ("riscv: Add KGDB support") Cc: Vincent Chen <vincent.chen@sifive.com> Link: https://patch.msgid.link/fde376f8-bcfd-bfe4-e467-07d8f7608d05@kernel.org Signed-off-by: Paul Walmsley <pjw@kernel.org>
Similarly to commit 8d09e2d ("arm64: patching: avoid early page_to_phys()"), avoid using phys_to_page() for the kernel address case in patch_map(). Since this is called from apply_boot_alternatives() in setup_arch(), and commit 4267739 ("arch, mm: consolidate initialization of SPARSE memory model") has moved sparse_init() to after setup_arch(), phys_to_page() is not available there yet, and it panics on boot with SPARSEMEM on RV32, which does not use SPARSEMEM_VMEMMAP. Reported-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Closes: https://lore.kernel.org/r/20260223144108-dcace0b9-02e8-4b67-a7ce-f263bed36f26@linutronix.de/ Fixes: 4267739 ("arch, mm: consolidate initialization of SPARSE memory model") Suggested-by: Mike Rapoport <rppt@kernel.org> Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn> Acked-by: Mike Rapoport (Microsoft) <rppt@kernel.org> Tested-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Link: https://patch.msgid.link/20260310-riscv-sparsemem-alternatives-fix-v1-1-659d5dd257e2@iscas.ac.cn [pjw@kernel.org: fix the subject line to align with the patch description] Signed-off-by: Paul Walmsley <pjw@kernel.org>
The BITS variable conveniently allows to simplify the assignment for UTS_MACHINE. Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com> Link: https://patch.msgid.link/20260313164012.1153936-2-u.kleine-koenig@baylibre.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
The BIT() macros is used by the validate_v_ptrace() test case, but not defined. Include linux/bits.h to pull in this definition. To ensure that the header in the kernel source is used, add tools/include to the header search path. Fixes: 30eb191 ("selftests: riscv: verify ptrace rejects invalid vector csr inputs") Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Reviewed-and-tested-by: Sergey Matyukevich <geomatsi@gmail.com> Link: https://patch.msgid.link/20260309-fix_selftests-v2-1-9d5a553a531e@gmail.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
BIT() is being used in ptrace.h without a definition, resulting in compilation errors in tools/testing/selftests/riscv/cfi/cfitests.c: cfitests.c:101:60: error: implicit declaration of function ‘BIT’ [-Wimplicit-function-declaration] 101 | if ((cfi_reg.cfi_status.cfi_state & CFI_ENABLE_MASK) != CFI_ENABLE_MASK) Include linux/bits.h to resolve this issue. Fixes: 2af7c9c ("riscv/ptrace: expose riscv CFI status and state via ptrace and in core files") Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Reviewed-by: Deepak Gupta <debug@rivosinc.com> Link: https://patch.msgid.link/20260309-fix_selftests-v2-3-9d5a553a531e@gmail.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
The cfi selftest was missing a license so add it. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Reviewed-by: Deepak Gupta <debug@rivosinc.com> Link: https://patch.msgid.link/20260309-fix_selftests-v2-4-9d5a553a531e@gmail.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
In the arch/riscv/Kconfig, the HOTPLUG_CPU depends on SMP, hence if the HOTPLUG_CPU is defined, the SMP has to be defined, it is not necessary to check SMP here. Signed-off-by: Hui Wang <hui.wang@canonical.com> Link: https://patch.msgid.link/20260304033403.238012-1-hui.wang@canonical.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
The cpu-hotplug.c only is built when CONFIG_HOTPLUG_CPU is defined, it is not needed to check HOTPLUG_CPU in this file. Signed-off-by: Hui Wang <hui.wang@canonical.com> Link: https://patch.msgid.link/20260304033403.238012-2-hui.wang@canonical.com [pjw@kernel.org: removed extra whitespace at EOF] Signed-off-by: Paul Walmsley <pjw@kernel.org>
Similar as commit 284922f ("x86: uaccess: don't use runtime-const rewriting in modules") does, make riscv's runtime const not usable by modules too, to "make sure this doesn't get forgotten the next time somebody wants to do runtime constant optimizations". The reason is well explained in the above commit: "The runtime-const infrastructure was never designed to handle the modular case, because the constant fixup is only done at boot time for core kernel code." Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Link: https://patch.msgid.link/20260221023731.3476-1-jszhang@kernel.org Signed-off-by: Paul Walmsley <pjw@kernel.org>
… support Andes cache driver is not only usable with the AX45MP CPU but can also be applied to other CPU within Andes platform (such as A27L2). To improve maintainability and support future SoCs, this patch performs a comprehensive refactoring to move away from model-specific naming. key changes include: - replaced AX45MP-specific Kconfig and function names with generic "ANDES" prefixes to support multiple CPU types - updated all L2-related identifiers, structs, and prefixes to "LLC" to accurately reflect its role as the system's last-level cache - moved UCCTL* CSR definitions to <linux/soc/andes/csr.h> - standardized L1D and LLC macro prefixes (ANDES_L1D_* and ANDES_LLC_*) for better clarity - renamed compatible strings from ax45mp-cache to generic llcache - rename ax45mp_cache.c to andes_llcache.c This is a structural refactoring; no functional behavior is changed. Signed-off-by: charles <dminus@andestech.com> Signed-off-by: Hui Min Mina Chou <minachou@andestech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
This patch cleans up the Andes LLC cache driver: - improved error handling in andes_cache_init() by using goto labels - updated andes_dma_cache_inv/wback() to check for !size instead of start == end - cache-line-size mismatch from an error to a warning - Use ALIGN and ALIGN_DOWN helpers instead of the alignment logic in andes_dma_cache_inv() and andes_dma_cache_wback(). Signed-off-by: Hui Min Mina Chou <minachou@andestech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Eliminate get_cpu() on !CONFIG_SMP and switch readl/writel to their relaxed variants to remove unnecessary fence instructions on I/O memory access. The platform specification defines all I/O regions are on channel 0 (point-to-point strongly ordered), so explicit fences are not required [1][2][3]. Explicit memory barriers (mb) are added before and after the CCTL loop to ensure overall memory consistency. Also fix hart ID mapping by switching to cpuid_to_hartid_map() instead of using the logical CPU ID directly. In AMP setups (e.g. Linux on Hart 1, RTOS on Hart 0), Linux sees itself as CPU 0 but must access Hart 1's CCTL registers, so using the logical ID would cause accidental interference with other cores. [1] platform spec 2.1.1: https://github.com/riscvarchive/riscv-platform-specs/blob/main/riscv-platform-spec.adoc?plain=1#L169 [2] privileged spec 3.6.5: https://github.com/riscv/riscv-isa-manual/blob/main/src/machine.adoc?plain=1#L2835 [3] riscv: asm/mmio.h: https://gitea.andestech.com/RD-SW/linux/src/branch/ast-v5_4_0-branch/arch/riscv/include/asm/mmio.h#L105 Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Signed-off-by: Hui Min Mina Chou <minachou@andestech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Introduce andes_cpu_cache_operation() to centralize address translation, alignment, and IRQ handling, removing the redundant wrappers andes_cpu_dcache_wb_range and andes_cpu_dcache_inval_range. This refactoring includes the following refinements: - Consolidates address translation, boundary alignment, and IRQ handling (local_irq_save/restore) into the central function. - Make IRQ handling per cache line instead of across the entire cache operation. - Cleans up redundant intermediate wrapper functions (andes_cpu_dcache_wb_range, andes_cpu_dcache_inval_range). - wback_inv was chaining wback + inv separately; use the hardware's native WBINVAL CCTL instead, which does both in one shot. Signed-off-by: Alex Chun-Ju Lin <alex749@andestech.com> Signed-off-by: Hui Min Mina Chou <minachou@andestech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The AX45MP-specific cache binding is renamed to a generic Last Level Cache (LLC) schema, as the driver now supports more Andes CPU cores beyond just AX45MP. Updated compatible strings: andestech,qilai-ax45mp-cache -> andestech,qilai-llcache renesas,r9a07g043f-ax45mp-cache -> renesas,r9a07g043f-llcache andestech,ax45mp-cache -> andestech,llcache Signed-off-by: Hui Min Mina Chou <minachou@andestech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Update the cache driver compatible strings from ax45mp-cache to llcache for both Qilai and RZ/Five platforms. This follows the Andes cache driver refactoring to use more generic Last Level Cache (LLC) naming. Signed-off-by: Hui Min Mina Chou <minachou@andestech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Here add maintainer information for Andes cache driver. Signed-off-by: Hui Min Mina Chou <minachou@andestech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[1/7] cache: ax45mp_cache: refactor cache driver for generic Andes platform support" |
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Patch 1: "[1/7] cache: ax45mp_cache: refactor cache driver for generic Andes platform support" |
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Patch 1: "[1/7] cache: ax45mp_cache: refactor cache driver for generic Andes platform support" |
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Patch 1: "[1/7] cache: ax45mp_cache: refactor cache driver for generic Andes platform support" |
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Patch 1: "[1/7] cache: ax45mp_cache: refactor cache driver for generic Andes platform support" |
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Patch 1: "[1/7] cache: ax45mp_cache: refactor cache driver for generic Andes platform support" |
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Patch 1: "[1/7] cache: ax45mp_cache: refactor cache driver for generic Andes platform support" |
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Patch 1: "[1/7] cache: ax45mp_cache: refactor cache driver for generic Andes platform support" |
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Patch 6: "[6/7] dts: riscv: update cache compatible strings to LLC" |
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Patch 6: "[6/7] dts: riscv: update cache compatible strings to LLC" |
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Patch 6: "[6/7] dts: riscv: update cache compatible strings to LLC" |
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Patch 6: "[6/7] dts: riscv: update cache compatible strings to LLC" |
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Patch 6: "[6/7] dts: riscv: update cache compatible strings to LLC" |
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Patch 6: "[6/7] dts: riscv: update cache compatible strings to LLC" |
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Patch 6: "[6/7] dts: riscv: update cache compatible strings to LLC" |
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Patch 6: "[6/7] dts: riscv: update cache compatible strings to LLC" |
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Patch 6: "[6/7] dts: riscv: update cache compatible strings to LLC" |
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Patch 6: "[6/7] dts: riscv: update cache compatible strings to LLC" |
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Patch 6: "[6/7] dts: riscv: update cache compatible strings to LLC" |
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Patch 6: "[6/7] dts: riscv: update cache compatible strings to LLC" |
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Patch 7: "[7/7] MAINTAINERS: Add maintainers for Andes cache driver" |
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Patch 7: "[7/7] MAINTAINERS: Add maintainers for Andes cache driver" |
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Patch 7: "[7/7] MAINTAINERS: Add maintainers for Andes cache driver" |
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Patch 7: "[7/7] MAINTAINERS: Add maintainers for Andes cache driver" |
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Patch 7: "[7/7] MAINTAINERS: Add maintainers for Andes cache driver" |
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Patch 7: "[7/7] MAINTAINERS: Add maintainers for Andes cache driver" |
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Patch 7: "[7/7] MAINTAINERS: Add maintainers for Andes cache driver" |
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Patch 7: "[7/7] MAINTAINERS: Add maintainers for Andes cache driver" |
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Patch 7: "[7/7] MAINTAINERS: Add maintainers for Andes cache driver" |
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Patch 7: "[7/7] MAINTAINERS: Add maintainers for Andes cache driver" |
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Patch 7: "[7/7] MAINTAINERS: Add maintainers for Andes cache driver" |
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Patch 7: "[7/7] MAINTAINERS: Add maintainers for Andes cache driver" |
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PR for series 1074514 applied to workflow__riscv__for-next
Name: refactor Andes cache driver for generic platform support
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1074514
Version: 1