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[PW_SID:1080731] [v2] riscv: smp: Align secondary_start_sbi to 4 bytes#1762

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[PW_SID:1080731] [v2] riscv: smp: Align secondary_start_sbi to 4 bytes#1762
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@linux-riscv-bot linux-riscv-bot commented Apr 13, 2026

PR for series 1080731 applied to workflow__riscv__fixes

Name: [v2] riscv: smp: Align secondary_start_sbi to 4 bytes
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1080731
Version: 2

@cp0613
riscv: smp: Align secondary_start_sbi to 4 bytes
c172b4f 
During SMP boot, the secondary_start_sbi address is passed to the
slave core via sbi_hsm_hart_start. In OpenSBI, this address is
written to STVEC in sbi_hart_switch_mode.

According to the privileged specification, the BASE field of STVEC
must always be aligned on a 4-byte boundary. However, System.map
reveals that secondary_start_sbi is not a 4-byte aligned address.

For example, the address of secondary_start_sbi is
0xffffffff80001066, and the disassembly is as follows:

Dump of assembler code from 0xffffffff80001052 to 0xffffffff8000107a:
   0xffffffff80001052 <_start+4178>:    c.nop   -11
   0xffffffff80001054 <_start+4180>:    auipc   gp,0x1a1f
   0xffffffff80001058 <_start+4184>:    addi    gp,gp,84
   0xffffffff8000105c <_start+4188>:    csrw    satp,a2
   0xffffffff80001060 <_start+4192>:    sfence.vma
   0xffffffff80001064 <_start+4196>:    ret
   0xffffffff80001066 <_start+4198>:    csrw    sie,zero
   0xffffffff8000106a <_start+4202>:    csrw    sip,zero
   0xffffffff8000106e <_start+4206>:    li      t0,2
   0xffffffff80001070 <_start+4208>:    csrw    scounteren,t0
   0xffffffff80001074 <_start+4212>:    auipc   gp,0x1a1f
   0xffffffff80001078 <_start+4216>:    addi    gp,gp,52

When writing to STVEC at address 0xffffffff80001066, the actual
write address is 0xffffffff80001064, corresponding to the address
of the previous ret instruction. This is unexpected, and if an
interrupt occurs at this point, it will cause unpredictable results.

However, secondary_start_sbi immediately masks all interrupts and
updates STVEC, so no problems occurred.

In summary, it is more reasonable to make secondary_start_sbi
satisfy 4-byte alignment.

Changes in v2:
 - Place `.align 2` inside `#ifdef CONFIG_SMP`, above the tag.
 - Add two Reviewed-by tags.
 - Based on Linux 7.0.

Reviewed-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
Reviewed-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org>
Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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linux-riscv-bot commented Apr 13, 2026

Patch 1: "[v2] riscv: smp: Align secondary_start_sbi to 4 bytes"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 136.57 seconds
Result: PASS

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linux-riscv-bot commented Apr 13, 2026

Patch 1: "[v2] riscv: smp: Align secondary_start_sbi to 4 bytes"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 1108.90 seconds
Result: PASS

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linux-riscv-bot commented Apr 13, 2026

Patch 1: "[v2] riscv: smp: Align secondary_start_sbi to 4 bytes"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1631.39 seconds
Result: PASS

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linux-riscv-bot commented Apr 13, 2026

Patch 1: "[v2] riscv: smp: Align secondary_start_sbi to 4 bytes"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 24.99 seconds
Result: PASS

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linux-riscv-bot commented Apr 13, 2026

Patch 1: "[v2] riscv: smp: Align secondary_start_sbi to 4 bytes"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 25.70 seconds
Result: PASS

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linux-riscv-bot commented Apr 13, 2026

Patch 1: "[v2] riscv: smp: Align secondary_start_sbi to 4 bytes"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 0.73 seconds
Result: PASS

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linux-riscv-bot commented Apr 13, 2026

Patch 1: "[v2] riscv: smp: Align secondary_start_sbi to 4 bytes"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 83.38 seconds
Result: PASS

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linux-riscv-bot commented Apr 13, 2026

Patch 1: "[v2] riscv: smp: Align secondary_start_sbi to 4 bytes"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.23 seconds
Result: PASS

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linux-riscv-bot commented Apr 13, 2026

Patch 1: "[v2] riscv: smp: Align secondary_start_sbi to 4 bytes"
kdoc
Desc: Detects for kdoc errors
Duration: 0.86 seconds
Result: PASS

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linux-riscv-bot commented Apr 13, 2026

Patch 1: "[v2] riscv: smp: Align secondary_start_sbi to 4 bytes"
module-param
Desc: Detect module_param changes
Duration: 0.24 seconds
Result: PASS

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linux-riscv-bot commented Apr 13, 2026

Patch 1: "[v2] riscv: smp: Align secondary_start_sbi to 4 bytes"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.22 seconds
Result: PASS

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linux-riscv-bot commented Apr 13, 2026

Patch 1: "[v2] riscv: smp: Align secondary_start_sbi to 4 bytes"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.30 seconds
Result: PASS

@linux-riscv-bot linux-riscv-bot deleted the pw1080731 branch April 21, 2026 01:53
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