[PW_SID:1080955] Add Linux RISC-V trace support via CoreSight by linux-riscv-bot · Pull Request #1764 · linux-riscv/linux

linux-riscv-bot · 2026-04-14T03:55:42Z

PR for series 1080955 applied to workflow__riscv__fixes

Name: Add Linux RISC-V trace support via CoreSight
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1080955
Version: 1

Enable CoreSight tracing support on RISC-V architecture by: - Adding RISC-V to Kconfig dependencies for CoreSight - Replacing ARM-specific memory barriers (isb, dmb) with RISC-V equivalents (local_flush_icache_all, __mb) - Removing ARM-specific header dependencies: perf/arm_pmu.h, asm/smp_plat.h - Adding PMU format attribute macros for cross-architecture support This allows CoreSight tracing infrastructure to work on RISC-V systems while maintaining compatibility with existing ARM/ARM64 implementations. Signed-off-by: liangzhen <zhen.liang@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Implement some common driver interfaces RISC-V trace where RISC-V trace components are instantiated by a common platform driver and a separate RISC-V trace driver for each type of RISC-V trace component. Signed-off-by: liangzhen <zhen.liang@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Add initial implementation of RISC-V trace encoder driver. The encoder is defined in the RISC-V Trace Control Interface specification. Signed-off-by: liangzhen <zhen.liang@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Add initial implementation of RISC-V trace funnel driver. The funnel is defined in the RISC-V Trace Control Interface specification. Signed-off-by: liangzhen <zhen.liang@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Add initial implementation of RISC-V trace ATB Bridge driver. The ATB Bridge is defined in the RISC-V Trace Control Interface specification. Signed-off-by: liangzhen <zhen.liang@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

…nnel Implement timestamp as a configurable sub-component for both encoder and funnel drivers. Signed-off-by: liangzhen <zhen.liang@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Define CORESIGHT_ETM_PMU_NAME based on architecture: - Set to "rvtrace" when CONFIG_RVTRACE is enabled - Default to "cs_etm" for ARM/ARM64 systems Signed-off-by: liangzhen <zhen.liang@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

This commit enhances the RISC-V performance tools by allowing the rvtrace PMU to be listed and selected when auxiliary trace support is enabled. Signed-off-by: liangzhen <zhen.liang@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Introduce the required auxiliary API functions allowing the perf core to interact with RISC-V trace perf driver. Signed-off-by: liangzhen <zhen.liang@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Add support for RISC-V Nexus Trace decoder based on the reference implementation from the RISC-V Nexus Trace specification. This includes a CoreSight frame deformatter to remove the trace formatter overhead. Signed-off-by: liangzhen <zhen.liang@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Add PLT header and entry size definitions for RISC-V architecture. RISC-V uses: - PLT header size: 32 bytes - PLT entry size: 16 bytes This allows perf to correctly identify and display PLT symbols instead of showing them as [unknown]. Signed-off-by: liangzhen <zhen.liang@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Add RISC-V trace decoder implementation and integrate it into perf's auxtrace infrastructure. This enables processing of RISC-V Nexus trace data through the standard perf auxtrace pipeline. Signed-off-by: liangzhen <zhen.liang@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

linux-riscv-bot · 2026-04-14T04:02:00Z

Patch 1: "[RFC,01/12] coresight: Add RISC-V support to CoreSight tracing"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 136.43 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T04:14:08Z

Patch 1: "[RFC,01/12] coresight: Add RISC-V support to CoreSight tracing"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 727.04 seconds
Result: ERROR
Output:

Redirect to /build/tmp.KIXHW37hii and /build/tmp.ZUleuubvgU
Tree base:
506e7f67b3724 ("Adding CI files")
Building the whole tree with the patch
error:
Warning: /build/tmpcykvxz8h/drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c:244 struct __packed mtk_mfg_opp_entry { __le32 freq_khz; __le32 voltage_core; __le32 voltage_sram; __le32 posdiv; __le32 voltage_margin; __le32 power_mw; }; error: Cannot parse struct or union!
/build/tmpcykvxz8h/include/linux/perf/arm_pmu.h:15:10: fatal error: 'asm/cputype.h' file not found
/build/tmpcykvxz8h/drivers/hwtracing/coresight/coresight-etm-cp14.c:11:10: fatal error: 'asm/hardware/cp14.h' file not found



real	12m0.953s
user	468m10.551s
sys	82m7.834s

linux-riscv-bot · 2026-04-14T04:30:39Z

Patch 1: "[RFC,01/12] coresight: Add RISC-V support to CoreSight tracing"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 989.74 seconds
Result: ERROR
Output:

Redirect to /build/tmp.rMUr4i0xpL and /build/tmp.P7dgO8Rrwb
Tree base:
506e7f67b3724 ("Adding CI files")
Building the whole tree with the patch
error:
Warning: /build/tmpcykvxz8h/drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c:244 struct __packed mtk_mfg_opp_entry { __le32 freq_khz; __le32 voltage_core; __le32 voltage_sram; __le32 posdiv; __le32 voltage_margin; __le32 power_mw; }; error: Cannot parse struct or union!
/build/tmpcykvxz8h/include/linux/perf/arm_pmu.h:15:10: fatal error: asm/cputype.h: No such file or directory
/build/tmpcykvxz8h/drivers/hwtracing/coresight/coresight-etm-cp14.c:11:10: fatal error: asm/hardware/cp14.h: No such file or directory



real	16m23.305s
user	648m56.949s
sys	100m14.371s

linux-riscv-bot · 2026-04-14T04:31:07Z

Patch 1: "[RFC,01/12] coresight: Add RISC-V support to CoreSight tracing"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 26.10 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T04:31:35Z

Patch 1: "[RFC,01/12] coresight: Add RISC-V support to CoreSight tracing"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 26.96 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T04:31:40Z

Patch 1: "[RFC,01/12] coresight: Add RISC-V support to CoreSight tracing"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 3.11 seconds
Result: ERROR
Output:

ERROR: Macros with complex values should be enclosed in parentheses
#106: FILE: drivers/hwtracing/coresight/coresight-etm-perf.h:61:
+#define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi)			\
+	(lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi

BUT SEE:

   do {} while (0) advice is over-stated in a few situations:

   The more obvious case is macros, like MODULE_PARM_DESC, invoked at
   file-scope, where C disallows code (it must be in functions).  See
   $exceptions if you have one to add by name.

   More troublesome is declarative macros used at top of new scope,
   like DECLARE_PER_CPU.  These might just compile with a do-while-0
   wrapper, but would be incorrect.  Most of these are handled by
   detecting struct,union,etc declaration primitives in $exceptions.

   Theres also macros called inside an if (block), which "return" an
   expression.  These cannot do-while, and need a ({}) wrapper.

   Enjoy this qualification while we work to improve our heuristics.

CHECK: Macro argument 'cfg' may be better as '(cfg)' to avoid precedence issues
#118: FILE: drivers/hwtracing/coresight/coresight-etm-perf.h:73:
+#define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi)			\
+	((((attr)->cfg) >> lo) & GENMASK_ULL(hi - lo, 0))

CHECK: Macro argument 'lo' may be better as '(lo)' to avoid precedence issues
#118: FILE: drivers/hwtracing/coresight/coresight-etm-perf.h:73:
+#define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi)			\
+	((((attr)->cfg) >> lo) & GENMASK_ULL(hi - lo, 0))

CHECK: Macro argument 'hi' may be better as '(hi)' to avoid precedence issues
#118: FILE: drivers/hwtracing/coresight/coresight-etm-perf.h:73:
+#define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi)			\
+	((((attr)->cfg) >> lo) & GENMASK_ULL(hi - lo, 0))

total: 1 errors, 0 warnings, 3 checks, 101 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit 40721832e809 ("coresight: Add RISC-V support to CoreSight tracing") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
CHECK: Macro argument 'cfg' may be better as '(cfg)' to avoid precedence issues
CHECK: Macro argument 'hi' may be better as '(hi)' to avoid precedence issues
CHECK: Macro argument 'lo' may be better as '(lo)' to avoid precedence issues
ERROR: Macros with complex values should be enclosed in parentheses

linux-riscv-bot · 2026-04-14T04:33:04Z

Patch 1: "[RFC,01/12] coresight: Add RISC-V support to CoreSight tracing"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 82.86 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T04:33:06Z

Patch 1: "[RFC,01/12] coresight: Add RISC-V support to CoreSight tracing"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.25 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T04:33:08Z

Patch 1: "[RFC,01/12] coresight: Add RISC-V support to CoreSight tracing"
kdoc
Desc: Detects for kdoc errors
Duration: 0.85 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T04:33:10Z

Patch 1: "[RFC,01/12] coresight: Add RISC-V support to CoreSight tracing"
module-param
Desc: Detect module_param changes
Duration: 0.28 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T04:33:12Z

Patch 1: "[RFC,01/12] coresight: Add RISC-V support to CoreSight tracing"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T04:33:14Z

Patch 1: "[RFC,01/12] coresight: Add RISC-V support to CoreSight tracing"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.32 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T04:35:44Z

Patch 2: "[RFC,02/12] coresight: Initial implementation of RISC-V trace driver"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 135.73 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T04:47:53Z

Patch 2: "[RFC,02/12] coresight: Initial implementation of RISC-V trace driver"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 728.09 seconds
Result: ERROR
Output:

Redirect to /build/tmp.P9bg9GxvNZ and /build/tmp.jNsSc1xn5J
Tree base:
40721832e809f ("coresight: Add RISC-V support to CoreSight tracing")
Building the whole tree with the patch
error:
Warning: /build/tmp7ufpv7hq/drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c:244 struct __packed mtk_mfg_opp_entry { __le32 freq_khz; __le32 voltage_core; __le32 voltage_sram; __le32 posdiv; __le32 voltage_margin; __le32 power_mw; }; error: Cannot parse struct or union!
/build/tmp7ufpv7hq/drivers/hwtracing/coresight/coresight-etm-cp14.c:11:10: fatal error: 'asm/hardware/cp14.h' file not found
/build/tmp7ufpv7hq/include/linux/perf/arm_pmu.h:15:10: fatal error: 'asm/cputype.h' file not found



real	12m2.021s
user	468m20.517s
sys	82m25.948s

linux-riscv-bot · 2026-04-14T05:04:28Z

Patch 2: "[RFC,02/12] coresight: Initial implementation of RISC-V trace driver"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 993.05 seconds
Result: ERROR
Output:

Redirect to /build/tmp.h56vode0Eb and /build/tmp.95XWfnbpM9
Tree base:
40721832e809f ("coresight: Add RISC-V support to CoreSight tracing")
Building the whole tree with the patch
error:
Warning: /build/tmp7ufpv7hq/drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c:244 struct __packed mtk_mfg_opp_entry { __le32 freq_khz; __le32 voltage_core; __le32 voltage_sram; __le32 posdiv; __le32 voltage_margin; __le32 power_mw; }; error: Cannot parse struct or union!
/build/tmp7ufpv7hq/include/linux/perf/arm_pmu.h:15:10: fatal error: asm/cputype.h: No such file or directory
/build/tmp7ufpv7hq/drivers/hwtracing/coresight/coresight-etm-cp14.c:11:10: fatal error: asm/hardware/cp14.h: No such file or directory



real	16m26.719s
user	649m49.564s
sys	100m47.980s

linux-riscv-bot · 2026-04-14T05:04:55Z

Patch 2: "[RFC,02/12] coresight: Initial implementation of RISC-V trace driver"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 25.19 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T05:05:23Z

Patch 2: "[RFC,02/12] coresight: Initial implementation of RISC-V trace driver"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 26.34 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T05:05:27Z

Patch 2: "[RFC,02/12] coresight: Initial implementation of RISC-V trace driver"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 2.72 seconds
Result: WARNING
Output:

WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#50: 
new file mode 100644

CHECK: Alignment should match open parenthesis
#118: FILE: drivers/hwtracing/coresight/rvtrace-core.c:64:
+	writel_relaxed(RVTRACE_COMPONENT_CTRL_ACTIVE_MASK,
+			comp->base + RVTRACE_COMPONENT_CTRL_OFFSET);

total: 0 errors, 1 warnings, 1 checks, 268 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit 2d175d9cfb23 ("coresight: Initial implementation of RISC-V trace driver") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 1 warnings, 1 checks, 268 lines checked
CHECK: Alignment should match open parenthesis
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?

linux-riscv-bot · 2026-04-14T09:37:44Z

Patch 10: "[RFC,10/12] perf tools: Add Nexus RISC-V Trace decoder"
kdoc
Desc: Detects for kdoc errors
Duration: 0.91 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T09:37:46Z

Patch 10: "[RFC,10/12] perf tools: Add Nexus RISC-V Trace decoder"
module-param
Desc: Detect module_param changes
Duration: 0.27 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T09:37:48Z

Patch 10: "[RFC,10/12] perf tools: Add Nexus RISC-V Trace decoder"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T09:37:50Z

Patch 10: "[RFC,10/12] perf tools: Add Nexus RISC-V Trace decoder"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.32 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T09:40:19Z

Patch 11: "[RFC,11/12] perf symbols: Add RISC-V PLT entry sizes"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 135.48 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T09:52:28Z

Patch 11: "[RFC,11/12] perf symbols: Add RISC-V PLT entry sizes"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 727.27 seconds
Result: ERROR
Output:

Redirect to /build/tmp.4CJIPNpFn2 and /build/tmp.SvJlEjUZNk
Tree base:
027f27fb641a4 ("perf tools: Add Nexus RISC-V Trace decoder")
Building the whole tree with the patch
error:
Warning: /build/tmpvd90sz5s/drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c:244 struct __packed mtk_mfg_opp_entry { __le32 freq_khz; __le32 voltage_core; __le32 voltage_sram; __le32 posdiv; __le32 voltage_margin; __le32 power_mw; }; error: Cannot parse struct or union!
/build/tmpvd90sz5s/include/linux/perf/arm_pmu.h:15:10: fatal error: 'asm/cputype.h' file not found
/build/tmpvd90sz5s/drivers/hwtracing/coresight/coresight-etm-cp14.c:11:10: fatal error: 'asm/hardware/cp14.h' file not found



real	12m1.134s
user	467m35.148s
sys	82m19.377s

linux-riscv-bot · 2026-04-14T10:09:01Z

Patch 11: "[RFC,11/12] perf symbols: Add RISC-V PLT entry sizes"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 991.23 seconds
Result: ERROR
Output:

Redirect to /build/tmp.evuW4Key2a and /build/tmp.spMpaSFrVd
Tree base:
027f27fb641a4 ("perf tools: Add Nexus RISC-V Trace decoder")
Building the whole tree with the patch
error:
Warning: /build/tmpvd90sz5s/drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c:244 struct __packed mtk_mfg_opp_entry { __le32 freq_khz; __le32 voltage_core; __le32 voltage_sram; __le32 posdiv; __le32 voltage_margin; __le32 power_mw; }; error: Cannot parse struct or union!
/build/tmpvd90sz5s/drivers/hwtracing/coresight/coresight-etm-cp14.c:11:10: fatal error: asm/hardware/cp14.h: No such file or directory
/build/tmpvd90sz5s/include/linux/perf/arm_pmu.h:15:10: fatal error: asm/cputype.h: No such file or directory



real	16m24.906s
user	649m3.552s
sys	100m55.358s

linux-riscv-bot · 2026-04-14T10:09:28Z

Patch 11: "[RFC,11/12] perf symbols: Add RISC-V PLT entry sizes"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 25.04 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T10:09:56Z

Patch 11: "[RFC,11/12] perf symbols: Add RISC-V PLT entry sizes"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 26.16 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T10:09:58Z

Patch 11: "[RFC,11/12] perf symbols: Add RISC-V PLT entry sizes"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 0.78 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T10:11:22Z

Patch 11: "[RFC,11/12] perf symbols: Add RISC-V PLT entry sizes"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 82.78 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T10:11:24Z

Patch 11: "[RFC,11/12] perf symbols: Add RISC-V PLT entry sizes"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.24 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T10:11:26Z

Patch 11: "[RFC,11/12] perf symbols: Add RISC-V PLT entry sizes"
kdoc
Desc: Detects for kdoc errors
Duration: 0.88 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T10:11:28Z

Patch 11: "[RFC,11/12] perf symbols: Add RISC-V PLT entry sizes"
module-param
Desc: Detect module_param changes
Duration: 0.27 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T10:11:30Z

Patch 11: "[RFC,11/12] perf symbols: Add RISC-V PLT entry sizes"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T10:11:32Z

Patch 11: "[RFC,11/12] perf symbols: Add RISC-V PLT entry sizes"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.32 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T10:14:02Z

Patch 12: "[RFC,12/12] perf tools: Integrate RISC-V trace decoder into auxtrace"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 135.85 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T10:26:11Z

Patch 12: "[RFC,12/12] perf tools: Integrate RISC-V trace decoder into auxtrace"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 728.02 seconds
Result: ERROR
Output:

Redirect to /build/tmp.9zb9nHK4sA and /build/tmp.3kPfzRGnr6
Tree base:
7f236ecd182d8 ("perf symbols: Add RISC-V PLT entry sizes")
Building the whole tree with the patch
error:
Warning: /build/tmp4kcx6pw3/drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c:244 struct __packed mtk_mfg_opp_entry { __le32 freq_khz; __le32 voltage_core; __le32 voltage_sram; __le32 posdiv; __le32 voltage_margin; __le32 power_mw; }; error: Cannot parse struct or union!
/build/tmp4kcx6pw3/drivers/hwtracing/coresight/coresight-etm-cp14.c:11:10: fatal error: 'asm/hardware/cp14.h' file not found
/build/tmp4kcx6pw3/include/linux/perf/arm_pmu.h:15:10: fatal error: 'asm/cputype.h' file not found



real	12m1.848s
user	468m15.995s
sys	82m24.274s

linux-riscv-bot · 2026-04-14T10:42:44Z

Patch 12: "[RFC,12/12] perf tools: Integrate RISC-V trace decoder into auxtrace"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 990.78 seconds
Result: ERROR
Output:

Redirect to /build/tmp.NOkzjaQzK5 and /build/tmp.QeRYoteScv
Tree base:
7f236ecd182d8 ("perf symbols: Add RISC-V PLT entry sizes")
Building the whole tree with the patch
error:
Warning: /build/tmp4kcx6pw3/drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c:244 struct __packed mtk_mfg_opp_entry { __le32 freq_khz; __le32 voltage_core; __le32 voltage_sram; __le32 posdiv; __le32 voltage_margin; __le32 power_mw; }; error: Cannot parse struct or union!
/build/tmp4kcx6pw3/drivers/hwtracing/coresight/coresight-etm-cp14.c:11:10: fatal error: asm/hardware/cp14.h: No such file or directory
/build/tmp4kcx6pw3/include/linux/perf/arm_pmu.h:15:10: fatal error: asm/cputype.h: No such file or directory



real	16m24.534s
user	648m5.640s
sys	100m57.192s

linux-riscv-bot · 2026-04-14T10:43:12Z

Patch 12: "[RFC,12/12] perf tools: Integrate RISC-V trace decoder into auxtrace"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 26.37 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T10:43:41Z

Patch 12: "[RFC,12/12] perf tools: Integrate RISC-V trace decoder into auxtrace"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 27.59 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T10:43:48Z

Patch 12: "[RFC,12/12] perf tools: Integrate RISC-V trace decoder into auxtrace"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 5.49 seconds
Result: WARNING
Output:

WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54: 
new file mode 100644

WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst
#173: FILE: tools/perf/util/rvtrace-decoder.c:115:
+		buffer[i] = ((volatile u8 *)virt_addr)[i];

WARNING: line length of 141 exceeds 100 columns
#227: FILE: tools/perf/util/rvtrace-decoder.c:169:
+		ui__warning_once("RISC-V Nexus Trace: Missing DSO. Use 'perf archive' or debuginfod to export data from the traced system.\n"

WARNING: line length of 105 exceeds 100 columns
#230: FILE: tools/perf/util/rvtrace-decoder.c:172:
+			pr_err("RISC-V Nexus Trace: Debug data not found for address %#"PRIx64" in %s\n",

CHECK: Concatenated strings should use spaces between elements
#230: FILE: tools/perf/util/rvtrace-decoder.c:172:
+			pr_err("RISC-V Nexus Trace: Debug data not found for address %#"PRIx64" in %s\n",

CHECK: Alignment should match open parenthesis
#231: FILE: tools/perf/util/rvtrace-decoder.c:173:
+			pr_err("RISC-V Nexus Trace: Debug data not found for address %#"PRIx64" in %s\n",
+				address,

CHECK: Please don't use multiple blank lines
#243: FILE: tools/perf/util/rvtrace-decoder.c:185:
+
+

CHECK: Lines should not end with a '('
#323: FILE: tools/perf/util/rvtrace-decoder.c:265:
+		pr_err(

WARNING: line length of 123 exceeds 100 columns
#404: FILE: tools/perf/util/rvtrace-decoder.c:346:
+			fprintf(stdout, "RISC-V Trace: A FIFO overrun has resulted in the loss of one or more messages\n");

CHECK: Unnecessary parentheses around 'queue->tid == tid'
#508: FILE: tools/perf/util/rvtrace-decoder.c:450:
+		if (rvtraceq && ((tid == -1) || (queue->tid == tid))) {

CHECK: Alignment should match open parenthesis
#782: FILE: tools/perf/util/rvtrace-decoder.c:724:
+static bool rvtrace_evsel_is_auxtrace(struct perf_session *session,
+					     struct evsel *evsel)

CHECK: No space is necessary after a cast
#833: FILE: tools/perf/util/rvtrace-decoder.c:775:
+	if (sample->time && (sample->time != (u64) -1))

CHECK: Alignment should match open parenthesis
#897: FILE: tools/perf/util/rvtrace-decoder.c:839:
+	color_fprintf(stdout, color,
+			". ... Trace Encoder Trace data: size %#zx bytes\n",

CHECK: braces {} should be used on all arms of this statement
#928: FILE: tools/perf/util/rvtrace-decoder.c:870:
+		if (is_pipe)
[...]
+		else {
[...]

CHECK: Unbalanced braces around else statement
#930: FILE: tools/perf/util/rvtrace-decoder.c:872:
+		else {

CHECK: Please don't use multiple blank lines
#949: FILE: tools/perf/util/rvtrace-decoder.c:891:
+
+

CHECK: No space is necessary after a cast
#1013: FILE: tools/perf/util/rvtrace-decoder.c:955:
+	ptr = (u64 *) auxtrace_info->priv;

CHECK: Alignment should match open parenthesis
#1048: FILE: tools/perf/util/rvtrace-decoder.c:990:
+		itrace_synth_opts__set_default(&rvtrace->synth_opts,
+			session->itrace_synth_opts->default_no_sample);

CHECK: No space is necessary after a cast
#1055: FILE: tools/perf/util/rvtrace-decoder.c:997:
+	rvtrace->pmu_type = (unsigned int) ((ptr[RVTRACE_PMU_TYPE_CPUS] >> 32) & 0xffffffff);

total: 0 errors, 5 warnings, 14 checks, 1067 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit 5af4ecf94a46 ("perf tools: Integrate RISC-V trace decoder into auxtrace") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 5 warnings, 14 checks, 1067 lines checked
CHECK: Alignment should match open parenthesis
CHECK: Concatenated strings should use spaces between elements
CHECK: Lines should not end with a '('
CHECK: No space is necessary after a cast
CHECK: Please don't use multiple blank lines
CHECK: Unbalanced braces around else statement
CHECK: Unnecessary parentheses around 'queue->tid == tid'
CHECK: braces {} should be used on all arms of this statement
WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
WARNING: line length of 105 exceeds 100 columns
WARNING: line length of 123 exceeds 100 columns
WARNING: line length of 141 exceeds 100 columns

linux-riscv-bot · 2026-04-14T10:45:14Z

Patch 12: "[RFC,12/12] perf tools: Integrate RISC-V trace decoder into auxtrace"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 83.67 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T10:45:16Z

Patch 12: "[RFC,12/12] perf tools: Integrate RISC-V trace decoder into auxtrace"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.24 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T10:45:18Z

Patch 12: "[RFC,12/12] perf tools: Integrate RISC-V trace decoder into auxtrace"
kdoc
Desc: Detects for kdoc errors
Duration: 0.85 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T10:45:20Z

Patch 12: "[RFC,12/12] perf tools: Integrate RISC-V trace decoder into auxtrace"
module-param
Desc: Detect module_param changes
Duration: 0.27 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T10:45:22Z

Patch 12: "[RFC,12/12] perf tools: Integrate RISC-V trace decoder into auxtrace"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2026-04-14T10:45:24Z

Patch 12: "[RFC,12/12] perf tools: Integrate RISC-V trace decoder into auxtrace"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.31 seconds
Result: PASS

lz-bro added 12 commits April 14, 2026 03:55

coresight: Add RISC-V Trace Funnel driver

def3d52

Add initial implementation of RISC-V trace funnel driver. The funnel is defined in the RISC-V Trace Control Interface specification. Signed-off-by: liangzhen <zhen.liang@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

coresight rvtrace: Add timestamp component support for encoder and fu…

9a81d93

…nnel Implement timestamp as a configurable sub-component for both encoder and funnel drivers. Signed-off-by: liangzhen <zhen.liang@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

perf tools: Add RISC-V trace PMU record capabilities

53fd55b

Introduce the required auxiliary API functions allowing the perf core to interact with RISC-V trace perf driver. Signed-off-by: liangzhen <zhen.liang@spacemit.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

linux-riscv-bot closed this Apr 22, 2026

linux-riscv-bot deleted the pw1080955 branch April 22, 2026 00:05

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