[PW_SID:1081887] Add interrupt controller for JHB100 SoC#1782
[PW_SID:1081887] Add interrupt controller for JHB100 SoC#1782linux-riscv-bot wants to merge 5 commits into
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…h8100 for jhb100 The StarFive JH8100 SoC was discontinued before production. The newly taped-out JHB100 SoC uses the same interrupt controller IP. Rename the binding file, compatible string, and MAINTAINERS entry from "jh8100" to "jhb100". In JHB100 SoC, The clocks and resets are not operated by users, but they exist in the hardware. Mark them as optional. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The StarFive JH8100 SoC was discontinued before production. The newly taped-out JHB100 SoC uses the same interrupt controller IP. Rename the driver file, Kconfig symbol, and internal references from "jh8100" to "jhb100" to accurately reflect the supported hardware. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Use devm_ interfaces to simplify resource release. Make clock and reset get optional as they are not used on the JHB100 SoC. Replace pr_ logging with dev_* logging. Use __free(kfree) cleanup attribute to auto-free irqc on error paths Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
StarFive JHB100 SoC interrupt controller actually supports 64 interrupt sources, the original code only supported up to 32. now it is extended to 64. Also use guard(raw_spinlock) to automatically release spinlocks. Signed-off-by: Mason Huo <mason.huo@starfivetech.com> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add irq_set_type() callback to support configuring interrupt trigger types (level high/low, edge rising/falling) for the JHB100 interrupt controller. Also add irq_ack() callabck as required by handle_edge_irq(). Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v2,1/5] dt-bindings: interrupt-controller: repurpose binding for unreleased jh8100 for jhb100" |
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Patch 1: "[v2,1/5] dt-bindings: interrupt-controller: repurpose binding for unreleased jh8100 for jhb100" |
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Patch 1: "[v2,1/5] dt-bindings: interrupt-controller: repurpose binding for unreleased jh8100 for jhb100" |
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Patch 1: "[v2,1/5] dt-bindings: interrupt-controller: repurpose binding for unreleased jh8100 for jhb100" |
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Patch 1: "[v2,1/5] dt-bindings: interrupt-controller: repurpose binding for unreleased jh8100 for jhb100" |
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Patch 1: "[v2,1/5] dt-bindings: interrupt-controller: repurpose binding for unreleased jh8100 for jhb100" |
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Patch 1: "[v2,1/5] dt-bindings: interrupt-controller: repurpose binding for unreleased jh8100 for jhb100" |
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Patch 1: "[v2,1/5] dt-bindings: interrupt-controller: repurpose binding for unreleased jh8100 for jhb100" |
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Patch 1: "[v2,1/5] dt-bindings: interrupt-controller: repurpose binding for unreleased jh8100 for jhb100" |
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Patch 1: "[v2,1/5] dt-bindings: interrupt-controller: repurpose binding for unreleased jh8100 for jhb100" |
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Patch 1: "[v2,1/5] dt-bindings: interrupt-controller: repurpose binding for unreleased jh8100 for jhb100" |
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Patch 1: "[v2,1/5] dt-bindings: interrupt-controller: repurpose binding for unreleased jh8100 for jhb100" |
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Patch 2: "[v2,2/5] irqchip/starfive: Rename jh8100 to jhb100" |
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Patch 2: "[v2,2/5] irqchip/starfive: Rename jh8100 to jhb100" |
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Patch 2: "[v2,2/5] irqchip/starfive: Rename jh8100 to jhb100" |
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Patch 2: "[v2,2/5] irqchip/starfive: Rename jh8100 to jhb100" |
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Patch 2: "[v2,2/5] irqchip/starfive: Rename jh8100 to jhb100" |
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Patch 2: "[v2,2/5] irqchip/starfive: Rename jh8100 to jhb100" |
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Patch 2: "[v2,2/5] irqchip/starfive: Rename jh8100 to jhb100" |
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Patch 2: "[v2,2/5] irqchip/starfive: Rename jh8100 to jhb100" |
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Patch 2: "[v2,2/5] irqchip/starfive: Rename jh8100 to jhb100" |
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Patch 2: "[v2,2/5] irqchip/starfive: Rename jh8100 to jhb100" |
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Patch 2: "[v2,2/5] irqchip/starfive: Rename jh8100 to jhb100" |
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Patch 2: "[v2,2/5] irqchip/starfive: Rename jh8100 to jhb100" |
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Patch 3: "[v2,3/5] irqchip/starfive: Use devm_ interfaces to simplify resource release" |
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Patch 3: "[v2,3/5] irqchip/starfive: Use devm_ interfaces to simplify resource release" |
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Patch 3: "[v2,3/5] irqchip/starfive: Use devm_ interfaces to simplify resource release" |
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Patch 3: "[v2,3/5] irqchip/starfive: Use devm_ interfaces to simplify resource release" |
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Patch 3: "[v2,3/5] irqchip/starfive: Use devm_ interfaces to simplify resource release" |
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Patch 4: "[v2,4/5] irqchip/starfive: Increase the interrupt source number up to 64" |
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Patch 4: "[v2,4/5] irqchip/starfive: Increase the interrupt source number up to 64" |
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Patch 4: "[v2,4/5] irqchip/starfive: Increase the interrupt source number up to 64" |
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Patch 4: "[v2,4/5] irqchip/starfive: Increase the interrupt source number up to 64" |
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Patch 4: "[v2,4/5] irqchip/starfive: Increase the interrupt source number up to 64" |
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Patch 4: "[v2,4/5] irqchip/starfive: Increase the interrupt source number up to 64" |
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Patch 4: "[v2,4/5] irqchip/starfive: Increase the interrupt source number up to 64" |
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Patch 4: "[v2,4/5] irqchip/starfive: Increase the interrupt source number up to 64" |
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Patch 4: "[v2,4/5] irqchip/starfive: Increase the interrupt source number up to 64" |
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Patch 4: "[v2,4/5] irqchip/starfive: Increase the interrupt source number up to 64" |
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Patch 4: "[v2,4/5] irqchip/starfive: Increase the interrupt source number up to 64" |
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Patch 4: "[v2,4/5] irqchip/starfive: Increase the interrupt source number up to 64" |
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Patch 5: "[v2,5/5] irqchip/starfive: Implement irq_set_type() and irq_ack() callbacks" |
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Patch 5: "[v2,5/5] irqchip/starfive: Implement irq_set_type() and irq_ack() callbacks" |
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Patch 5: "[v2,5/5] irqchip/starfive: Implement irq_set_type() and irq_ack() callbacks" |
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Patch 5: "[v2,5/5] irqchip/starfive: Implement irq_set_type() and irq_ack() callbacks" |
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Patch 5: "[v2,5/5] irqchip/starfive: Implement irq_set_type() and irq_ack() callbacks" |
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Patch 5: "[v2,5/5] irqchip/starfive: Implement irq_set_type() and irq_ack() callbacks" |
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Patch 5: "[v2,5/5] irqchip/starfive: Implement irq_set_type() and irq_ack() callbacks" |
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Patch 5: "[v2,5/5] irqchip/starfive: Implement irq_set_type() and irq_ack() callbacks" |
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Patch 5: "[v2,5/5] irqchip/starfive: Implement irq_set_type() and irq_ack() callbacks" |
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Patch 5: "[v2,5/5] irqchip/starfive: Implement irq_set_type() and irq_ack() callbacks" |
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Patch 5: "[v2,5/5] irqchip/starfive: Implement irq_set_type() and irq_ack() callbacks" |
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Patch 5: "[v2,5/5] irqchip/starfive: Implement irq_set_type() and irq_ack() callbacks" |
PR for series 1081887 applied to workflow__riscv__fixes
Name: Add interrupt controller for JHB100 SoC
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1081887
Version: 2