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[PW_SID:1083898] [V5] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup#1802

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[PW_SID:1083898] [V5] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup#1802
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@linux-riscv-bot linux-riscv-bot commented Apr 21, 2026

PR for series 1083898 applied to workflow__riscv__fixes

Name: [V5] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1083898
Version: 5

Linux RISC-V bot and others added 2 commits April 5, 2026 01:35
Adding CI files
506e7f6
@guoren83
riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup
9bd563c 
The early version of XuanTie C910 core has a store merge buffer
delay problem. The store merge buffer could improve the store queue
performance by merging multi-store requests, but when there are not
continued store requests, the prior single store request would be
waiting in the store queue for a long time. That would cause
significant problems for communication between multi-cores. This
problem was found on sg2042 & th1520 platforms with the qspinlock
lock torture test.

So appending a fence w.o could immediately flush the store merge
buffer and let other cores see the write result.

This will apply the WRITE_ONCE errata to handle the non-standard
behavior via appending a fence w.o instruction for WRITE_ONCE().

This problem is only observed on the sg2042 hardware platform by
running the lock_torture test program for half an hour. The problem
was not found in the user space application, because interrupt can
break the livelock.

Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Leonardo Bras <leobras@redhat.com>
Reviewed-by: Inochi Amaoto <inochiama@gmail.com>
Tested-by: Han Gao <gaohan@iscas.ac.cn>
Tested-by: Yao Zi <me@ziyao.cc>
Cc: Chen Wang <unicorn_wang@outlook.com>
Cc: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Cc: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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linux-riscv-bot commented Apr 21, 2026

Patch 1: "[V5] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 136.03 seconds
Result: PASS

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linux-riscv-bot commented Apr 21, 2026

Patch 1: "[V5] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 2192.61 seconds
Result: PASS

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linux-riscv-bot commented Apr 21, 2026

Patch 1: "[V5] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 2965.98 seconds
Result: PASS

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linux-riscv-bot commented Apr 21, 2026

Patch 1: "[V5] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 24.80 seconds
Result: PASS

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linux-riscv-bot commented Apr 21, 2026

Patch 1: "[V5] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 26.06 seconds
Result: PASS

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linux-riscv-bot commented Apr 21, 2026

Patch 1: "[V5] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 2.87 seconds
Result: WARNING
Output:

WARNING: 'cant' may be misspelled - perhaps 'can't'?
#64: FILE: arch/riscv/Kconfig.errata:167:
+	  cant problems for communication between multi-cores. Appending a
 	  ^^^^

WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#125: 
new file mode 100644

WARNING: Single statement macros should not use a do {} while (0) loop
#142: FILE: arch/riscv/include/asm/rwonce.h:13:
+#define write_once_fence()				\
+do {							\
+	asm volatile(ALTERNATIVE(			\
+		"nop",					\
+		"fence w, o",				\
+		THEAD_VENDOR_ID,			\
+		ERRATA_THEAD_WRITE_ONCE,		\
+		CONFIG_ERRATA_THEAD_WRITE_ONCE)		\
+		: : : "memory");			\
+} while (0)

WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst
#155: FILE: arch/riscv/include/asm/rwonce.h:26:
+	*(volatile typeof(x) *)&(x) = (val);		\

total: 0 errors, 4 warnings, 0 checks, 108 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit 9bd563c13182 ("riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 4 warnings, 0 checks, 108 lines checked
WARNING: 'cant' may be misspelled - perhaps 'can't'?
WARNING: Single statement macros should not use a do {} while (0) loop
WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?

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linux-riscv-bot commented Apr 21, 2026

Patch 1: "[V5] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 83.83 seconds
Result: PASS

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linux-riscv-bot commented Apr 21, 2026

Patch 1: "[V5] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.24 seconds
Result: PASS

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linux-riscv-bot commented Apr 21, 2026

Patch 1: "[V5] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup"
kdoc
Desc: Detects for kdoc errors
Duration: 0.88 seconds
Result: PASS

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linux-riscv-bot commented Apr 21, 2026

Patch 1: "[V5] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup"
module-param
Desc: Detect module_param changes
Duration: 0.25 seconds
Result: PASS

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linux-riscv-bot commented Apr 21, 2026

Patch 1: "[V5] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.23 seconds
Result: PASS

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linux-riscv-bot commented Apr 21, 2026

Patch 1: "[V5] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.30 seconds
Result: PASS

@linux-riscv-bot linux-riscv-bot force-pushed the workflow__riscv__fixes branch from 506e7f6 to 01805bc Compare April 24, 2026 14:53
@linux-riscv-bot linux-riscv-bot deleted the pw1083898 branch April 29, 2026 00:22
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