[PW_SID:1084338] microchip core-qspi gpio-cs fixes + cleanup#1805
[PW_SID:1084338] microchip core-qspi gpio-cs fixes + cleanup#1805linux-riscv-bot wants to merge 6 commits into
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The coreQSPI IP supports only a single chip select, which is automagically operated by the hardware - set low when the transmit buffer first gets written to and set high when the number of bytes written to the TOTALBYTES field of the FRAMES register have been sent on the bus. Additional devices must use GPIOs for their chip selects. It was reported to me that if there are two devices attached to this QSPI controller that the in-built chip select is set low while linux tries to access the device attached to the GPIO. This went undetected as the boards that connected multiple devices to the SPI controller all exclusively used GPIOs for chip selects, not relying on the built-in chip select at all. It turns out that this was because the built-in chip select, when controlled automagically, is set low when active and high when inactive, thereby ruling out its use for active-high devices or devices that need to transmit with the chip select disabled. Modify the driver so that it controls chip select directly, retaining the behaviour for mem_ops of setting the chip select active for the entire duration of the transfer in the exec_op callback. For regular transfers, implement the set_cs callback for the core to use. As part of this, the existing setup callback, mchp_coreqspi_setup_op(), is removed. Modifying the CLKIDLE field is not safe to do during operation when there are multiple devices, so this code is removed entirely. Setting the MASTER and ENABLE fields is something that can be done once at probe, it doesn't need to be re-run for each device. Instead the new setup callback sets the built-in chip select to its inactive state for active-low devices, as the reset value of the chip select in software controlled mode is low. Fixes: 8f9cf02 ("spi: microchip-core-qspi: Add regular transfers") Fixes: 8596124 ("spi: microchip-core-qspi: Add support for microchip fpga qspi controllers") CC: stable@vger.kernel.org Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
…ead-only dual/quad operations The core will deal with reads by creating clock cycles itself, there's no need to generate clock cycles by transmitting garbage data at the driver level. Further, transmitting garbage data just bricks the transfer since QSPI doesn't have a dedicated master-out line like MOSI in regular SPI. I'm not entirely sure if the transfer is bricked because of the garbage data being transmitted on the bus or because the core loses track of whether it is supposed to be sending or receiving data. Fixes: 8f9cf02 ("spi: microchip-core-qspi: Add regular transfers") CC: stable@vger.kernel.org Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
…ead of which controller When prepare_message callbacks fail, the SPI core already reports which controller the failure happened on. The corresponding code in the mem_ops portion of the driver already reports the device a timeout occurred on, so make the regular part of the driver do the same. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
I noticed this define was incorrect, it should be UpperAddress, but in renaming it it became clear there were actually no users. Just get rid of it. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Remove inline markings from a number of functions that are called as part of mem ops callbacks. None of them are either particularly trivial or sensitive to overhead of a function call. Just let the compiler decide what to do with them. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v1,1/5] spi: microchip-core-qspi: control built-in cs manually" |
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Patch 1: "[v1,1/5] spi: microchip-core-qspi: control built-in cs manually" |
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Patch 1: "[v1,1/5] spi: microchip-core-qspi: control built-in cs manually" |
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Patch 1: "[v1,1/5] spi: microchip-core-qspi: control built-in cs manually" |
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Patch 1: "[v1,1/5] spi: microchip-core-qspi: control built-in cs manually" |
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Patch 1: "[v1,1/5] spi: microchip-core-qspi: control built-in cs manually" |
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Patch 1: "[v1,1/5] spi: microchip-core-qspi: control built-in cs manually" |
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Patch 1: "[v1,1/5] spi: microchip-core-qspi: control built-in cs manually" |
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Patch 1: "[v1,1/5] spi: microchip-core-qspi: control built-in cs manually" |
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Patch 1: "[v1,1/5] spi: microchip-core-qspi: control built-in cs manually" |
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Patch 1: "[v1,1/5] spi: microchip-core-qspi: control built-in cs manually" |
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Patch 1: "[v1,1/5] spi: microchip-core-qspi: control built-in cs manually" |
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Patch 2: "[v1,2/5] spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations" |
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Patch 2: "[v1,2/5] spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations" |
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Patch 2: "[v1,2/5] spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations" |
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Patch 2: "[v1,2/5] spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations" |
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Patch 2: "[v1,2/5] spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations" |
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Patch 2: "[v1,2/5] spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations" |
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Patch 2: "[v1,2/5] spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations" |
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Patch 2: "[v1,2/5] spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations" |
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Patch 2: "[v1,2/5] spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations" |
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Patch 2: "[v1,2/5] spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations" |
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Patch 2: "[v1,2/5] spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations" |
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Patch 2: "[v1,2/5] spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations" |
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Patch 3: "[v1,3/5] spi: microchip-core-qspi: report device on which timeout occured instead of which controller" |
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Patch 3: "[v1,3/5] spi: microchip-core-qspi: report device on which timeout occured instead of which controller" |
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Patch 3: "[v1,3/5] spi: microchip-core-qspi: report device on which timeout occured instead of which controller" |
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Patch 4: "[v1,4/5] spi: microchip-core-qspi: remove an unused define" |
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Patch 4: "[v1,4/5] spi: microchip-core-qspi: remove an unused define" |
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Patch 4: "[v1,4/5] spi: microchip-core-qspi: remove an unused define" |
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Patch 4: "[v1,4/5] spi: microchip-core-qspi: remove an unused define" |
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Patch 4: "[v1,4/5] spi: microchip-core-qspi: remove an unused define" |
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Patch 4: "[v1,4/5] spi: microchip-core-qspi: remove an unused define" |
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Patch 4: "[v1,4/5] spi: microchip-core-qspi: remove an unused define" |
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Patch 4: "[v1,4/5] spi: microchip-core-qspi: remove an unused define" |
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Patch 4: "[v1,4/5] spi: microchip-core-qspi: remove an unused define" |
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Patch 4: "[v1,4/5] spi: microchip-core-qspi: remove an unused define" |
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Patch 4: "[v1,4/5] spi: microchip-core-qspi: remove an unused define" |
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Patch 4: "[v1,4/5] spi: microchip-core-qspi: remove an unused define" |
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Patch 5: "[v1,5/5] spi: microchip-core-qspi: remove some inline markings" |
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Patch 5: "[v1,5/5] spi: microchip-core-qspi: remove some inline markings" |
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Patch 5: "[v1,5/5] spi: microchip-core-qspi: remove some inline markings" |
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Patch 5: "[v1,5/5] spi: microchip-core-qspi: remove some inline markings" |
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Patch 5: "[v1,5/5] spi: microchip-core-qspi: remove some inline markings" |
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Patch 5: "[v1,5/5] spi: microchip-core-qspi: remove some inline markings" |
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Patch 5: "[v1,5/5] spi: microchip-core-qspi: remove some inline markings" |
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Patch 5: "[v1,5/5] spi: microchip-core-qspi: remove some inline markings" |
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Patch 5: "[v1,5/5] spi: microchip-core-qspi: remove some inline markings" |
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Patch 5: "[v1,5/5] spi: microchip-core-qspi: remove some inline markings" |
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Patch 5: "[v1,5/5] spi: microchip-core-qspi: remove some inline markings" |
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Patch 5: "[v1,5/5] spi: microchip-core-qspi: remove some inline markings" |
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PR for series 1084338 applied to workflow__riscv__fixes
Name: microchip core-qspi gpio-cs fixes + cleanup
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1084338
Version: 1