[PW_SID:1086857] iommu/riscv: Add hardware dirty tracking for second-stage domains#1830
[PW_SID:1086857] iommu/riscv: Add hardware dirty tracking for second-stage domains#1830linux-riscv-bot wants to merge 12 commits into
Conversation
Add support for Sv39x4/Sv48x4/Sv57x4 Second-stage page tables used by the RISC-V IOMMU iohgatp register. The x4 root page table is 16 KiB instead of the usual 4 KiB, covering 2 extra GPA bits (hw_max_vasz_lg2 = 41/50/59). Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Report RISC-V IOMMU capabilities required by VFIO subsystem to enable PCIe device assignment. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The parameter will be increased when we need to set up more bit fields in the device context. Use a data structure to wrap them up. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
This patch adds a ID Allocator for GSCID and a wrap for setting up GSCID in IOTLB invalidation command. Set up iohgatp to enable second stage table and flush stage-2 table if the GSCID is set. The GSCID of domain should be freed when release domain. GSCID will be allocated for parent domain in nested IOMMU process. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Enable KVM/VFIO support on RISC-V architecture. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Replace .domain_alloc_paging with .domain_alloc_paging_flags so callers can pass allocation flags to select the appropriate page-table type. When IOMMU_HWPT_ALLOC_NEST_PARENT or IOMMU_HWPT_ALLOC_DIRTY_TRACKING is set in @flags, allocate a second-stage (iohgatp) domain. When @flags is 0 the behaviour is identical to the previous domain_alloc_paging: first-stage (iosatp) domain. Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
When mapping writable pages, the RISC-V format code currently pre-sets the PTE D bit unconditionally. If hardware dirty tracking is active (DC.tc.GADE set), the IOMMU sets D autonomously on the first write. Pre-setting D makes every new mapping appear dirty immediately and breaks dirty tracking. Introduce PT_FEAT_RISCV_DIRTY_TRACKING_ACTIVE and, when set, leave D cleared for new writable mappings so hardware can capture the first write. Keep pre-setting D when dirty tracking is inactive. Only meaningful for second-stage (iohgatp) page tables. Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add hardware dirty tracking support for second-stage (iohgatp) domains
used in KVM VFIO device pass-through.
The RISC-V IOMMU can automatically set the dirty bit in PTEs on write
access when DC.tc.GADE is set and the hardware has AMO_HWAD capability.
Wire this up to the iommufd dirty tracking interface:
- riscv_iommu_set_dirty_tracking(): Walks all bonds of the domain and
sets or clears DC.tc.GADE in each device context entry.
- riscv_iommu_dirty_ops: Exposes set_dirty_tracking and the generic
page-table read_and_clear_dirty via IOMMU_PT_DIRTY_OPS(riscv_64).
- domain_alloc_paging_flags: Assigns dirty_ops to second-stage domains
when AMO_HWAD is advertised in hardware capabilities.
- riscv_iommu_capable: Reports IOMMU_CAP_DIRTY_TRACKING when
AMO_HWAD is present.
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Previously, only IOTINVAL.VMA was issued, which is insufficient for second-stage address translation consistency. Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Implement the three dirty-tracking hooks required by the generic page
table framework for the RISC-V format:
pt_entry_is_write_dirty():
Check the D bit (bit 7) in the PTE.
pt_entry_make_write_clean():
Clear the D bit across the full contiguous range.
pt_entry_make_write_dirty():
Atomically set D via try_cmpxchg64() on a single PTE.
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
This patch implements .hw_info operation and the related data structures for passing the IOMMU hardware capabilities for iommufd. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
|
Patch 1: "[RFC,01/11] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
|
Patch 1: "[RFC,01/11] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
|
Patch 1: "[RFC,01/11] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
|
Patch 1: "[RFC,01/11] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
|
Patch 1: "[RFC,01/11] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
|
Patch 1: "[RFC,01/11] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
|
Patch 1: "[RFC,01/11] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
|
Patch 1: "[RFC,01/11] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
|
Patch 1: "[RFC,01/11] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
|
Patch 1: "[RFC,01/11] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
|
Patch 1: "[RFC,01/11] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
|
Patch 1: "[RFC,01/11] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
|
Patch 2: "[RFC,02/11] iommu/riscv: report iommu capabilities" |
|
Patch 2: "[RFC,02/11] iommu/riscv: report iommu capabilities" |
|
Patch 2: "[RFC,02/11] iommu/riscv: report iommu capabilities" |
50e3f1e to
8cbc176
Compare
|
Patch 2: "[RFC,02/11] iommu/riscv: report iommu capabilities" |
|
Patch 2: "[RFC,02/11] iommu/riscv: report iommu capabilities" |
|
Patch 10: "[RFC,10/11] iommupt: Add RISC-V dirty tracking PTE ops" |
|
Patch 11: "[RFC,11/11] iommu/riscv: support nested iommu for getting iommu hardware information" |
|
Patch 11: "[RFC,11/11] iommu/riscv: support nested iommu for getting iommu hardware information" |
|
Patch 11: "[RFC,11/11] iommu/riscv: support nested iommu for getting iommu hardware information" |
|
Patch 11: "[RFC,11/11] iommu/riscv: support nested iommu for getting iommu hardware information" |
|
Patch 11: "[RFC,11/11] iommu/riscv: support nested iommu for getting iommu hardware information" |
|
Patch 11: "[RFC,11/11] iommu/riscv: support nested iommu for getting iommu hardware information" |
|
Patch 11: "[RFC,11/11] iommu/riscv: support nested iommu for getting iommu hardware information" |
|
Patch 11: "[RFC,11/11] iommu/riscv: support nested iommu for getting iommu hardware information" |
|
Patch 11: "[RFC,11/11] iommu/riscv: support nested iommu for getting iommu hardware information" |
|
Patch 11: "[RFC,11/11] iommu/riscv: support nested iommu for getting iommu hardware information" |
|
Patch 11: "[RFC,11/11] iommu/riscv: support nested iommu for getting iommu hardware information" |
|
Patch 11: "[RFC,11/11] iommu/riscv: support nested iommu for getting iommu hardware information" |
9cacb03 to
8635215
Compare
PR for series 1086857 applied to workflow
Name: iommu/riscv: Add hardware dirty tracking for second-stage domains
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1086857
Version: 1