[PW_SID:1087431] [v2] riscv: mm: fix SWIOTLB initialization for systems with DRAM above 4GB#1839
[PW_SID:1087431] [v2] riscv: mm: fix SWIOTLB initialization for systems with DRAM above 4GB#1839linux-riscv-bot wants to merge 3 commits into
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…_TYPED_FUNC_START After commit 67bdd7b ("riscv: Split out measure_cycles() for reuse") and commit c03ad15 ("riscv: Reuse measure_cycles() in check_vector_unaligned_access()"), there are CFI failure when booting kernels with CONFIG_CFI=y: CFI failure at measure_cycles+0x38/0xe0 (target: __riscv_copy_words_unaligned+0x0/0x50; expected type: ...) CFI failure at measure_cycles+0x38/0xe0 (target: __riscv_copy_vec_words_unaligned+0x0/0x24; expected type: ...) The __riscv_copy_*_unaligned() functions are now called indirectly but they are not defined with SYM_TYPED_FUNC_START, which is required for assembly functions called indirectly from C to pass CFI checking. Switch to SYM_TYPED_FUNC_START to clear up the CFI failures. Fixes: 67bdd7b ("riscv: Split out measure_cycles() for reuse") Fixes: c03ad15 ("riscv: Reuse measure_cycles() in check_vector_unaligned_access()") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Sami Tolvanen <samitolvanen@google.com> Reviewed-by: Nam Cao <namcao@linutronix.de> Link: https://patch.msgid.link/20260406-measure_cycles-cfi-failure-v1-1-03e0234ae02f@kernel.org Signed-off-by: Paul Walmsley <pjw@kernel.org>
On RISC-V platforms where the entire physical memory (DRAM) resides above the 32-bit address space (i.e., above dma32_phys_limit), the current SWIOTLB initialization logic fails. This patch addresses two interconnected issues on such platforms: 1. Incorrect 32-bit DMA bounce assumption: The existing condition `max_pfn > PFN_DOWN(dma32_phys_limit)` assumes that a 32-bit DMA bounce buffer is required simply because the maximum PFN exceeds the 32-bit limit. However, if all DRAM starts above 4GB, no memory exists below the limit to satisfy this allocation. Fix this by adding a check to ensure `memblock_start_of_DRAM()` is actually below the 32-bit limit before enforcing 32-bit SWIOTLB. 2. kmalloc() bounce buffer allocation failure on non-coherent systems: For non-coherent hardware, a bounce buffer is still mandatory for cache-line-aligned kmalloc(), even if 32-bit DMA bouncing is skipped. Without the `SWIOTLB_ANY` flag, swiotlb_init() defaults to allocating from low memory, which fails completely when DRAM only exists in high memory. By appending `SWIOTLB_ANY` to swiotlb_flags, the allocator is permitted to allocate this alignment buffer from high memory. With this patch, systems with non-coherent DMA and DRAM entirely above 4GB can successfully map the software IO TLB in high memory and boot normally. Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.dev> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v2] riscv: mm: fix SWIOTLB initialization for systems with DRAM above 4GB" |
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Patch 1: "[v2] riscv: mm: fix SWIOTLB initialization for systems with DRAM above 4GB" |
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Patch 1: "[v2] riscv: mm: fix SWIOTLB initialization for systems with DRAM above 4GB" |
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Patch 1: "[v2] riscv: mm: fix SWIOTLB initialization for systems with DRAM above 4GB" |
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Patch 1: "[v2] riscv: mm: fix SWIOTLB initialization for systems with DRAM above 4GB" |
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Patch 1: "[v2] riscv: mm: fix SWIOTLB initialization for systems with DRAM above 4GB" |
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Patch 1: "[v2] riscv: mm: fix SWIOTLB initialization for systems with DRAM above 4GB" |
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Patch 1: "[v2] riscv: mm: fix SWIOTLB initialization for systems with DRAM above 4GB" |
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Patch 1: "[v2] riscv: mm: fix SWIOTLB initialization for systems with DRAM above 4GB" |
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Patch 1: "[v2] riscv: mm: fix SWIOTLB initialization for systems with DRAM above 4GB" |
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Patch 1: "[v2] riscv: mm: fix SWIOTLB initialization for systems with DRAM above 4GB" |
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Patch 1: "[v2] riscv: mm: fix SWIOTLB initialization for systems with DRAM above 4GB" |
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PR for series 1087431 applied to workflow__riscv__fixes
Name: [v2] riscv: mm: fix SWIOTLB initialization for systems with DRAM above 4GB
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1087431
Version: 2