[PW_SID:1087459] riscv, bpf: Fix signed operations and add 32 bit atomics#1840
[PW_SID:1087459] riscv, bpf: Fix signed operations and add 32 bit atomics#1840linux-riscv-bot wants to merge 5 commits into
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…_TYPED_FUNC_START After commit 67bdd7b ("riscv: Split out measure_cycles() for reuse") and commit c03ad15 ("riscv: Reuse measure_cycles() in check_vector_unaligned_access()"), there are CFI failure when booting kernels with CONFIG_CFI=y: CFI failure at measure_cycles+0x38/0xe0 (target: __riscv_copy_words_unaligned+0x0/0x50; expected type: ...) CFI failure at measure_cycles+0x38/0xe0 (target: __riscv_copy_vec_words_unaligned+0x0/0x24; expected type: ...) The __riscv_copy_*_unaligned() functions are now called indirectly but they are not defined with SYM_TYPED_FUNC_START, which is required for assembly functions called indirectly from C to pass CFI checking. Switch to SYM_TYPED_FUNC_START to clear up the CFI failures. Fixes: 67bdd7b ("riscv: Split out measure_cycles() for reuse") Fixes: c03ad15 ("riscv: Reuse measure_cycles() in check_vector_unaligned_access()") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Sami Tolvanen <samitolvanen@google.com> Reviewed-by: Nam Cao <namcao@linutronix.de> Link: https://patch.msgid.link/20260406-measure_cycles-cfi-failure-v1-1-03e0234ae02f@kernel.org Signed-off-by: Paul Walmsley <pjw@kernel.org>
The current rv32 bpf jit compiler incorrectly treats BPF_SDIV and BPF_SMOD as unsigned operations. The BPF instruction set allows signed division and modulo by reusing the BPF_DIV and BPF_MOD opcodes with the instruction offset set to 1. Update the emit_alu_r32() function to accept an 'is_sdiv' variable and emit the correct div and rem instructions when the offset is 1. Before this patch: [ 44.161771] test_bpf: #165 ALU_SDIV_X: -6 / 2 = -3 jited:1 ret 2147483645 != -3 (0x7ffffffd != 0xfffffffd)FAIL (1 times) [ 44.167385] test_bpf: #166 ALU_SDIV_K: -6 / 2 = -3 jited:1 ret 2147483645 != -3 (0x7ffffffd != 0xfffffffd)FAIL (1 times) [ 44.171053] test_bpf: #169 ALU_SMOD_X: -7 % 2 = -1 jited:1 ret 1 != -1 (0x1 != 0xffffffff)FAIL (1 times) [ 44.172081] test_bpf: #170 ALU_SMOD_K: -7 % 2 = -1 jited:1 ret 1 != -1 (0x1 != 0xffffffff)FAIL (1 times) After this patch: [ 16.002192] test_bpf: #165 ALU_SDIV_X: -6 / 2 = -3 jited:1 95 PASS [ 16.002983] test_bpf: #166 ALU_SDIV_K: -6 / 2 = -3 jited:1 1059 PASS [ 16.017167] test_bpf: #169 ALU_SMOD_X: -7 % 2 = -1 jited:1 136 PASS [ 16.023002] test_bpf: #170 ALU_SMOD_K: -7 % 2 = -1 jited:1 109 PASS Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The current rv32 bpf jit compiler incorrectly treats BPF_MOVSX as a standard zero-extended move operation. The bpf instruction set allows sign-extension moves by reusing the BPF_MOV opcode with the instruction offset set to 8, 16, or 32. Update the bpf_jit_emit_insn() function to check the offset field for both ALU and ALU64 MOV operations. If the offset is non-zero, emit the correct slli and srai instructions to perform the sign extension. Before this patch: [ 19.549705] test_bpf: #82 ALU_MOVSX | BPF_B jited:1 ret 2 != 1 (0x2 != 0x1)FAIL (1 times) [ 19.551354] test_bpf: #83 ALU_MOVSX | BPF_H jited:1 ret 2 != 1 (0x2 != 0x1)FAIL (1 times) [ 19.552576] test_bpf: #84 ALU64_MOVSX | BPF_B jited:1 ret 2 != 1 (0x2 != 0x1)FAIL (1 times) [ 19.553542] test_bpf: #85 ALU64_MOVSX | BPF_H jited:1 ret 2 != 1 (0x2 != 0x1)FAIL (1 times) [ 19.554807] test_bpf: #86 ALU64_MOVSX | BPF_W jited:1 ret 2 != 1 (0x2 != 0x1)FAIL (1 times) After this patch: [ 17.931172] test_bpf: #82 ALU_MOVSX | BPF_B jited:1 125 PASS [ 17.932198] test_bpf: #83 ALU_MOVSX | BPF_H jited:1 124 PASS [ 17.933039] test_bpf: #84 ALU64_MOVSX | BPF_B jited:1 124 PASS [ 17.933918] test_bpf: #85 ALU64_MOVSX | BPF_H jited:1 124 PASS [ 17.934751] test_bpf: #86 ALU64_MOVSX | BPF_W jited:1 122 PASS Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The RV32 BPF JIT compiler currently only supports the BPF_ADD atomic operation. Other 32 bit atomic operations (and, or, xor, xchg) and their BPF_FETCH variants are not supported and gracefully fall back to the interpreter. Since the RISC-V A extension is required for Linux on RV32, we can natively support these 32-bit BPF atomic operations by mapping them directly to the corresponding RISC-V amo*.w instructions. Implement BPF_ADD, BPF_AND, BPF_OR, BPF_XOR, and BPF_XCHG with and without BPF_FETCH. BPF_CMPXCHG requires a more complex lr.w/sc.w loop and is left to fall back to the interpreter. Before this patch: [ 138.862161] test_bpf: Summary: 1054 PASSED, 0 FAILED, [843/1042 JIT'ed] After this patch: [ 157.024124] test_bpf: Summary: 1054 PASSED, 0 FAILED, [902/1042 JIT'ed] Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[bpf-next,1/3] riscv, bpf: Fix support for BPF_SDIV and BPF_SMOD in RV32 JIT" |
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Patch 1: "[bpf-next,1/3] riscv, bpf: Fix support for BPF_SDIV and BPF_SMOD in RV32 JIT" |
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Patch 1: "[bpf-next,1/3] riscv, bpf: Fix support for BPF_SDIV and BPF_SMOD in RV32 JIT" |
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Patch 1: "[bpf-next,1/3] riscv, bpf: Fix support for BPF_SDIV and BPF_SMOD in RV32 JIT" |
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Patch 1: "[bpf-next,1/3] riscv, bpf: Fix support for BPF_SDIV and BPF_SMOD in RV32 JIT" |
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Patch 1: "[bpf-next,1/3] riscv, bpf: Fix support for BPF_SDIV and BPF_SMOD in RV32 JIT" |
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Patch 1: "[bpf-next,1/3] riscv, bpf: Fix support for BPF_SDIV and BPF_SMOD in RV32 JIT" |
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Patch 1: "[bpf-next,1/3] riscv, bpf: Fix support for BPF_SDIV and BPF_SMOD in RV32 JIT" |
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Patch 1: "[bpf-next,1/3] riscv, bpf: Fix support for BPF_SDIV and BPF_SMOD in RV32 JIT" |
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Patch 1: "[bpf-next,1/3] riscv, bpf: Fix support for BPF_SDIV and BPF_SMOD in RV32 JIT" |
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Patch 1: "[bpf-next,1/3] riscv, bpf: Fix support for BPF_SDIV and BPF_SMOD in RV32 JIT" |
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Patch 1: "[bpf-next,1/3] riscv, bpf: Fix support for BPF_SDIV and BPF_SMOD in RV32 JIT" |
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Patch 2: "[bpf-next,2/3] riscv, bpf: Fix support for BPF_MOVSX in RV32 JIT" |
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Patch 2: "[bpf-next,2/3] riscv, bpf: Fix support for BPF_MOVSX in RV32 JIT" |
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Patch 2: "[bpf-next,2/3] riscv, bpf: Fix support for BPF_MOVSX in RV32 JIT" |
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Patch 2: "[bpf-next,2/3] riscv, bpf: Fix support for BPF_MOVSX in RV32 JIT" |
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Patch 2: "[bpf-next,2/3] riscv, bpf: Fix support for BPF_MOVSX in RV32 JIT" |
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Patch 2: "[bpf-next,2/3] riscv, bpf: Fix support for BPF_MOVSX in RV32 JIT" |
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Patch 2: "[bpf-next,2/3] riscv, bpf: Fix support for BPF_MOVSX in RV32 JIT" |
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Patch 2: "[bpf-next,2/3] riscv, bpf: Fix support for BPF_MOVSX in RV32 JIT" |
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Patch 2: "[bpf-next,2/3] riscv, bpf: Fix support for BPF_MOVSX in RV32 JIT" |
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Patch 2: "[bpf-next,2/3] riscv, bpf: Fix support for BPF_MOVSX in RV32 JIT" |
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Patch 2: "[bpf-next,2/3] riscv, bpf: Fix support for BPF_MOVSX in RV32 JIT" |
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Patch 2: "[bpf-next,2/3] riscv, bpf: Fix support for BPF_MOVSX in RV32 JIT" |
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Patch 3: "[bpf-next,3/3] riscv, bpf: Add 32 bit atomic operations to RV32 JIT" |
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Patch 3: "[bpf-next,3/3] riscv, bpf: Add 32 bit atomic operations to RV32 JIT" |
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Patch 3: "[bpf-next,3/3] riscv, bpf: Add 32 bit atomic operations to RV32 JIT" |
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Patch 3: "[bpf-next,3/3] riscv, bpf: Add 32 bit atomic operations to RV32 JIT" |
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Patch 3: "[bpf-next,3/3] riscv, bpf: Add 32 bit atomic operations to RV32 JIT" |
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Patch 3: "[bpf-next,3/3] riscv, bpf: Add 32 bit atomic operations to RV32 JIT" |
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Patch 3: "[bpf-next,3/3] riscv, bpf: Add 32 bit atomic operations to RV32 JIT" |
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Patch 3: "[bpf-next,3/3] riscv, bpf: Add 32 bit atomic operations to RV32 JIT" |
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Patch 3: "[bpf-next,3/3] riscv, bpf: Add 32 bit atomic operations to RV32 JIT" |
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Patch 3: "[bpf-next,3/3] riscv, bpf: Add 32 bit atomic operations to RV32 JIT" |
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Patch 3: "[bpf-next,3/3] riscv, bpf: Add 32 bit atomic operations to RV32 JIT" |
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Patch 3: "[bpf-next,3/3] riscv, bpf: Add 32 bit atomic operations to RV32 JIT" |
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PR for series 1087459 applied to workflow__riscv__fixes
Name: riscv, bpf: Fix signed operations and add 32 bit atomics
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1087459
Version: 1