[PW_SID:1091007] iommu/riscv: Add hardware dirty tracking for second-stage domains#1880
[PW_SID:1091007] iommu/riscv: Add hardware dirty tracking for second-stage domains#1880linux-riscv-bot wants to merge 11 commits into
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Add support for Sv39x4/Sv48x4/Sv57x4 Second-stage page tables used by the RISC-V IOMMU iohgatp register. The x4 root page table is 16 KiB instead of the usual 4 KiB, covering 2 extra GPA bits (hw_max_vasz_lg2 = 41/50/59). Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Implement the three dirty-tracking hooks required by the generic page
table framework for the RISC-V format:
pt_entry_is_write_dirty():
Check the D bit (bit 7) in the PTE.
pt_entry_make_write_clean():
Clear the D bit across the full contiguous range.
pt_entry_make_write_dirty():
Atomically set D via try_cmpxchg64() on a single PTE.
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Report RISC-V IOMMU capabilities required by VFIO subsystem to enable PCIe device assignment. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The parameter will be increased when we need to set up more bit fields in the device context. Use a data structure to wrap them up. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
This patch adds a ID Allocator for GSCID and a wrap for setting up GSCID in IOTLB invalidation command. Set up iohgatp to enable second stage table and flush stage-2 table if the GSCID is set. The GSCID of domain should be freed when release domain. GSCID will be allocated for parent domain in nested IOMMU process. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Enable KVM/VFIO support on RISC-V architecture. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Replace .domain_alloc_paging with .domain_alloc_paging_flags so callers can pass allocation flags to select the appropriate page-table type. When IOMMU_HWPT_ALLOC_NEST_PARENT or IOMMU_HWPT_ALLOC_DIRTY_TRACKING is set in @flags, allocate a second-stage (iohgatp) domain. When @flags is 0 the behaviour is identical to the previous domain_alloc_paging: first-stage (iosatp) domain. Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Pre-enable RISCV_IOMMU_DC_TC_GADE in the device context when attaching a second-stage domain, if the IOMMU supports AMO_HWAD. Software pre-populates second-stage page tables with D set, so enabling GADE by default does not change normal behavior. When dirty tracking is enabled, iommufd clears the pre-set D bits and GADE becomes necessary for hardware to update the dirty bit on write access. This avoids toggling GADE dynamically and keeps device context setup consistent with second-stage domain attachment. Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add hardware dirty tracking support for second-stage (iohgatp) domains
used in KVM VFIO device pass-through.
The RISC-V IOMMU can automatically set the dirty bit in PTEs on write
access when DC.tc.GADE is set and the hardware has AMO_HWAD capability.
Wire this up to the iommufd dirty tracking interface:
- riscv_iommu_set_dirty_tracking(): Always enabled dirty tracking for
second-stage domain.
- riscv_iommu_dirty_ops: Exposes set_dirty_tracking and the generic
page-table read_and_clear_dirty via IOMMU_PT_DIRTY_OPS(riscv_64).
- domain_alloc_paging_flags: Assigns dirty_ops to second-stage domains
when AMO_HWAD is advertised in hardware capabilities.
- riscv_iommu_capable: Reports IOMMU_CAP_DIRTY_TRACKING when
AMO_HWAD is present.
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Previously, only IOTINVAL.VMA was issued, which is insufficient for second-stage address translation consistency. Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[RFC,v2,01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
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Patch 1: "[RFC,v2,01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
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Patch 1: "[RFC,v2,01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
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Patch 1: "[RFC,v2,01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
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Patch 1: "[RFC,v2,01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
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Patch 1: "[RFC,v2,01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
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Patch 1: "[RFC,v2,01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
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Patch 1: "[RFC,v2,01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
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Patch 1: "[RFC,v2,01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
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Patch 1: "[RFC,v2,01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
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Patch 1: "[RFC,v2,01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
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Patch 1: "[RFC,v2,01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support" |
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Patch 2: "[RFC,v2,02/10] iommupt: Add RISC-V dirty tracking PTE ops" |
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Patch 2: "[RFC,v2,02/10] iommupt: Add RISC-V dirty tracking PTE ops" |
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Patch 2: "[RFC,v2,02/10] iommupt: Add RISC-V dirty tracking PTE ops" |
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Patch 2: "[RFC,v2,02/10] iommupt: Add RISC-V dirty tracking PTE ops" |
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Patch 2: "[RFC,v2,02/10] iommupt: Add RISC-V dirty tracking PTE ops" |
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Patch 2: "[RFC,v2,02/10] iommupt: Add RISC-V dirty tracking PTE ops" |
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Patch 2: "[RFC,v2,02/10] iommupt: Add RISC-V dirty tracking PTE ops" |
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Patch 8: "[RFC,v2,08/10] iommu/riscv: Pre-enable GADE for second-stage domains" |
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Patch 8: "[RFC,v2,08/10] iommu/riscv: Pre-enable GADE for second-stage domains" |
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Patch 9: "[RFC,v2,09/10] iommu/riscv: Add dirty tracking support for second-stage domains" |
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Patch 9: "[RFC,v2,09/10] iommu/riscv: Add dirty tracking support for second-stage domains" |
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Patch 9: "[RFC,v2,09/10] iommu/riscv: Add dirty tracking support for second-stage domains" |
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Patch 9: "[RFC,v2,09/10] iommu/riscv: Add dirty tracking support for second-stage domains" |
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Patch 9: "[RFC,v2,09/10] iommu/riscv: Add dirty tracking support for second-stage domains" |
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Patch 9: "[RFC,v2,09/10] iommu/riscv: Add dirty tracking support for second-stage domains" |
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Patch 9: "[RFC,v2,09/10] iommu/riscv: Add dirty tracking support for second-stage domains" |
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Patch 9: "[RFC,v2,09/10] iommu/riscv: Add dirty tracking support for second-stage domains" |
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Patch 9: "[RFC,v2,09/10] iommu/riscv: Add dirty tracking support for second-stage domains" |
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Patch 9: "[RFC,v2,09/10] iommu/riscv: Add dirty tracking support for second-stage domains" |
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Patch 9: "[RFC,v2,09/10] iommu/riscv: Add dirty tracking support for second-stage domains" |
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Patch 9: "[RFC,v2,09/10] iommu/riscv: Add dirty tracking support for second-stage domains" |
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Patch 10: "[RFC,v2,10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries" |
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Patch 10: "[RFC,v2,10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries" |
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Patch 10: "[RFC,v2,10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries" |
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Patch 10: "[RFC,v2,10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries" |
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Patch 10: "[RFC,v2,10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries" |
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Patch 10: "[RFC,v2,10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries" |
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Patch 10: "[RFC,v2,10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries" |
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Patch 10: "[RFC,v2,10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries" |
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Patch 10: "[RFC,v2,10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries" |
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Patch 10: "[RFC,v2,10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries" |
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Patch 10: "[RFC,v2,10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries" |
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Patch 10: "[RFC,v2,10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries" |
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PR for series 1091007 applied to workflow__riscv__fixes
Name: iommu/riscv: Add hardware dirty tracking for second-stage domains
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1091007
Version: 2