[PW_SID:1091690] Support non-leaf and range invalidation features in RISC-V#1888
[PW_SID:1091690] Support non-leaf and range invalidation features in RISC-V#1888linux-riscv-bot wants to merge 9 commits into
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Use in-line member documentation and add some small clarifications to the members. This is preparation to add more members. - Note that pgsize is only used by arm-smmuv3 - Note that freelist is only used by iommupt - Reword queued to emphasize the flush-all behavior Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add a struct to keep track of all the things that are pending to be merged into the gather. The way gather merging works, the pending range is checked against the current gather, and the current gather can be flushed before the pending things are added. Thus, if new things have to be recorded in the gather they need to be kept in the pending struct until after the gather is optionally flushed. The next patch adds new items to the gather and the pending struct. Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Generating the ARM SMMUv3 and RISC-V invalidation commands optimally requires some additional details from iommupt: - leaf_levels_bitmap is used to compute the ARM Range Invalidation Table Top Level hint - leaf_levels_bitmap is also used to compute the stride when generating single invalidations to invalidate once per leaf - table_levels_bitmap also computes the ARM TTL for future cases when there are no leaves Put these under a feature since only two drivers need to calculate them. This is also useful for the coming kunit iotlb invalidation test to know more about what invalidation is happening. Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
…inval RISC-V can use the information from PT_FEAT_DETAILED_GATHER to compute the best stride to generate the single TLB invalidations. Pass the gather down to the lower functions and create a full-range gather for the flush-all callback. Reviewed-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Replace the per-page IOTLB invalidation loop with stride-based invalidation that uses the level bitmaps from iommu_iotlb_gather. Pre-calculate the invalidation information before running over the bonds loop as it is the same for every entry. The lowest set bit in the PT_FEAT_DETAILED_GATHER bitmaps indicates the stride. This design ignores the SVNAPOT contiguous pages on the assumption that they still have to be individually invalidated like ARM requires, though it is not clear from the spec. Replace the 2M cutoff for global invalidation with a 512 command limit. This is the same for a 4k stride and now scales with the stride size. Reviewed-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Non-leaf invalidation allows the single invalidate command to also clear the walk cache. If NL is available, set the NL bit if the gather indicates tables have been changed. The stride is already calculated properly. Reviewed-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The command queue entry format is 128 bits. Follow the pattern of the other drivers and encode the 64 bit dword number in the macro itself. RISC-V further has similarly named macros that are not field layout macros, but field content macros which won't get a new number. Overall this is clearer to understand the code and check for errors like using the wrong macro in the wrong spot. Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Use the RISC-V IOMMU Address Range Invalidation extension (capabilities.S, spec section 9.3) to invalidate an IOVA range with a single IOTINVAL.VMA command using NAPOT-encoded addressing. One iommu_iotlb_gather maps to one NAPOT invalidation command. The smallest power-of-two aligned range covering the gather is used since over-invalidation is always safe. S and NL seem to be orthogonal in the spec, so if NL is not supported then global invalidation is probably always going to happen as wiping a large range without a table change is not common. Reviewed-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v2,1/8] iommu: Split the kdoc comment for struct iommu_iotlb_gather" |
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Patch 1: "[v2,1/8] iommu: Split the kdoc comment for struct iommu_iotlb_gather" |
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Patch 1: "[v2,1/8] iommu: Split the kdoc comment for struct iommu_iotlb_gather" |
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Patch 1: "[v2,1/8] iommu: Split the kdoc comment for struct iommu_iotlb_gather" |
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Patch 1: "[v2,1/8] iommu: Split the kdoc comment for struct iommu_iotlb_gather" |
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Patch 1: "[v2,1/8] iommu: Split the kdoc comment for struct iommu_iotlb_gather" |
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Patch 1: "[v2,1/8] iommu: Split the kdoc comment for struct iommu_iotlb_gather" |
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Patch 1: "[v2,1/8] iommu: Split the kdoc comment for struct iommu_iotlb_gather" |
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Patch 1: "[v2,1/8] iommu: Split the kdoc comment for struct iommu_iotlb_gather" |
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Patch 1: "[v2,1/8] iommu: Split the kdoc comment for struct iommu_iotlb_gather" |
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Patch 1: "[v2,1/8] iommu: Split the kdoc comment for struct iommu_iotlb_gather" |
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Patch 1: "[v2,1/8] iommu: Split the kdoc comment for struct iommu_iotlb_gather" |
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Patch 2: "[v2,2/8] iommupt: Add struct iommupt_pending_gather" |
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Patch 2: "[v2,2/8] iommupt: Add struct iommupt_pending_gather" |
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Patch 2: "[v2,2/8] iommupt: Add struct iommupt_pending_gather" |
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Patch 2: "[v2,2/8] iommupt: Add struct iommupt_pending_gather" |
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Patch 2: "[v2,2/8] iommupt: Add struct iommupt_pending_gather" |
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Patch 2: "[v2,2/8] iommupt: Add struct iommupt_pending_gather" |
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Patch 2: "[v2,2/8] iommupt: Add struct iommupt_pending_gather" |
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Patch 2: "[v2,2/8] iommupt: Add struct iommupt_pending_gather" |
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Patch 2: "[v2,2/8] iommupt: Add struct iommupt_pending_gather" |
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Patch 6: "[v2,6/8] iommu/riscv: Add RISCV_IOMMU_CAPABILITIES_NL" |
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Patch 6: "[v2,6/8] iommu/riscv: Add RISCV_IOMMU_CAPABILITIES_NL" |
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Patch 7: "[v2,7/8] iommu/riscv: Include the dword number in RISCV_IOMMU_CMD macros" |
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Patch 7: "[v2,7/8] iommu/riscv: Include the dword number in RISCV_IOMMU_CMD macros" |
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Patch 7: "[v2,7/8] iommu/riscv: Include the dword number in RISCV_IOMMU_CMD macros" |
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Patch 7: "[v2,7/8] iommu/riscv: Include the dword number in RISCV_IOMMU_CMD macros" |
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Patch 7: "[v2,7/8] iommu/riscv: Include the dword number in RISCV_IOMMU_CMD macros" |
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Patch 7: "[v2,7/8] iommu/riscv: Include the dword number in RISCV_IOMMU_CMD macros" |
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Patch 7: "[v2,7/8] iommu/riscv: Include the dword number in RISCV_IOMMU_CMD macros" |
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Patch 7: "[v2,7/8] iommu/riscv: Include the dword number in RISCV_IOMMU_CMD macros" |
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Patch 7: "[v2,7/8] iommu/riscv: Include the dword number in RISCV_IOMMU_CMD macros" |
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Patch 7: "[v2,7/8] iommu/riscv: Include the dword number in RISCV_IOMMU_CMD macros" |
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Patch 7: "[v2,7/8] iommu/riscv: Include the dword number in RISCV_IOMMU_CMD macros" |
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Patch 7: "[v2,7/8] iommu/riscv: Include the dword number in RISCV_IOMMU_CMD macros" |
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Patch 8: "[v2,8/8] iommu/riscv: Add NAPOT range invalidation support" |
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Patch 8: "[v2,8/8] iommu/riscv: Add NAPOT range invalidation support" |
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Patch 8: "[v2,8/8] iommu/riscv: Add NAPOT range invalidation support" |
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Patch 8: "[v2,8/8] iommu/riscv: Add NAPOT range invalidation support" |
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Patch 8: "[v2,8/8] iommu/riscv: Add NAPOT range invalidation support" |
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Patch 8: "[v2,8/8] iommu/riscv: Add NAPOT range invalidation support" |
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Patch 8: "[v2,8/8] iommu/riscv: Add NAPOT range invalidation support" |
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Patch 8: "[v2,8/8] iommu/riscv: Add NAPOT range invalidation support" |
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Patch 8: "[v2,8/8] iommu/riscv: Add NAPOT range invalidation support" |
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Patch 8: "[v2,8/8] iommu/riscv: Add NAPOT range invalidation support" |
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Patch 8: "[v2,8/8] iommu/riscv: Add NAPOT range invalidation support" |
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Patch 8: "[v2,8/8] iommu/riscv: Add NAPOT range invalidation support" |
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PR for series 1091690 applied to workflow__riscv__fixes
Name: Support non-leaf and range invalidation features in RISC-V
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1091690
Version: 2