[PW_SID:1091815] iommu/riscv: Enable IOMMU_DMA#1890
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When IOMMU_DMA is enabled, devices get paging domains and MSI writes to IMSIC interrupt files must be handled correctly in the s-stage. As the device always writes to the host physical IMSIC addresses, which the IMSIC irqchip programs directly, install s-stage identity mappings for the host IMSICs. But, use IOMMU_RESV_DIRECT_RELAXABLE since the 1:1 mappings aren't required for device assignment. Loop over the cpus rather than imsic groups to handle asymmetric configurations. Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
With iommu/riscv driver available we can enable IOMMU_DMA support for RISC-V architecture. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[1/2] iommu/riscv: Map IMSIC addresses for paging domains" |
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Patch 1: "[1/2] iommu/riscv: Map IMSIC addresses for paging domains" |
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Patch 1: "[1/2] iommu/riscv: Map IMSIC addresses for paging domains" |
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Patch 1: "[1/2] iommu/riscv: Map IMSIC addresses for paging domains" |
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Patch 1: "[1/2] iommu/riscv: Map IMSIC addresses for paging domains" |
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Patch 1: "[1/2] iommu/riscv: Map IMSIC addresses for paging domains" |
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Patch 1: "[1/2] iommu/riscv: Map IMSIC addresses for paging domains" |
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Patch 1: "[1/2] iommu/riscv: Map IMSIC addresses for paging domains" |
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Patch 1: "[1/2] iommu/riscv: Map IMSIC addresses for paging domains" |
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Patch 1: "[1/2] iommu/riscv: Map IMSIC addresses for paging domains" |
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Patch 1: "[1/2] iommu/riscv: Map IMSIC addresses for paging domains" |
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Patch 1: "[1/2] iommu/riscv: Map IMSIC addresses for paging domains" |
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Patch 2: "[2/2] iommu/dma: enable IOMMU_DMA for RISC-V" |
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Patch 2: "[2/2] iommu/dma: enable IOMMU_DMA for RISC-V" |
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Patch 2: "[2/2] iommu/dma: enable IOMMU_DMA for RISC-V" |
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Patch 2: "[2/2] iommu/dma: enable IOMMU_DMA for RISC-V" |
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Patch 2: "[2/2] iommu/dma: enable IOMMU_DMA for RISC-V" |
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Patch 2: "[2/2] iommu/dma: enable IOMMU_DMA for RISC-V" |
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Patch 2: "[2/2] iommu/dma: enable IOMMU_DMA for RISC-V" |
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Patch 2: "[2/2] iommu/dma: enable IOMMU_DMA for RISC-V" |
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Patch 2: "[2/2] iommu/dma: enable IOMMU_DMA for RISC-V" |
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Patch 2: "[2/2] iommu/dma: enable IOMMU_DMA for RISC-V" |
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Patch 2: "[2/2] iommu/dma: enable IOMMU_DMA for RISC-V" |
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Patch 2: "[2/2] iommu/dma: enable IOMMU_DMA for RISC-V" |
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PR for series 1091815 applied to workflow__riscv__fixes
Name: iommu/riscv: Enable IOMMU_DMA
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1091815
Version: 1