[PW_SID:1092025] riscv: add SBI Supervisor Software Events support#1897
[PW_SID:1092025] riscv: add SBI Supervisor Software Events support#1897linux-riscv-bot wants to merge 6 commits into
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Add needed definitions for SBI Supervisor Software Events extension [1]. This extension enables the SBI to inject events into supervisor software much like ARM SDEI. [1] https://lists.riscv.org/g/tech-prs/message/515 Signed-off-by: Clément Léger <cleger@rivosinc.com> Co-developed-by: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com> Signed-off-by: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The SBI SSE extension allows the supervisor software to be notified by the SBI of specific events that are not maskable. The context switch is handled partially by the firmware which will save registers a6 and a7. When entering kernel we can rely on these 2 registers to setup the stack and save all the registers. Since SSE events can be delivered at any time to the kernel, including during exception handling, we need a way to locate the current_task for context tracking. On RISC-V, it is stored in scratch when in user space or tp when in kernel space (in which case SSCRATCH is zero). But at the beginning of exception handling, SSCRATCH is used to swap tp and check the origin of the exception. If interrupted at that point, then, there is no way to reliably know where is located the current task_struct. Even checking the interruption location won't work as SSE event can be nested on top of each other so the original interruption site might be lost at some point. In order to retrieve it reliably, store the current task in an additional __sse_entry_task per_cpu array. This array is then used to retrieve the current task based on the hart ID that is passed to the SSE event handler in a6. That being said, the way the current task struct is stored should probably be reworked to find a better reliable alternative. Since each event (and each CPU for local events) have their own context and can preempt each other, allocate a stack (and a shadow stack if needed) for each of them (and for each cpu for local events). The SSE handler runs as a synthetic handler episode, but completion must resume the context that was interrupted by the SSE event. Preserve stvec and, when the hypervisor extension is present, hstatus across do_sse() so the handler episode does not leak trap-vector or virtualization state into the interrupted context. When completing the event, if we were coming from kernel with interrupts disabled, simply return there. If coming from userspace or kernel with interrupts enabled, simulate an interrupt exception by setting IE_SIE in CSR_IP to allow delivery of signals to user task. For instance this can happen when a RAS event has been generated by a user application and a SIGBUS has been sent to a task. Signed-off-by: Clément Léger <cleger@rivosinc.com> Co-developed-by: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com> Signed-off-by: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add a driver-level interface for RISC-V SSE support. The interface lets Linux clients register handlers and enable, disable and complete SSE events. It will be used by PMU and GHES drivers. Co-developed-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Signed-off-by: Clément Léger <cleger@rivosinc.com> Co-developed-by: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com> Signed-off-by: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
In order to use SSE within PMU drivers, register an SSE handler for the local PMU event. Reuse the existing overflow IRQ handler and pass appropriate pt_regs. Add a config option RISCV_PMU_SBI_SSE to select event delivery via SSE events. When the SSE path is used, also honor the return value from perf_event_overflow(). If perf core throttles or disables an event, do not immediately restart the overflowed counters from the SSE handler. Signed-off-by: Clément Léger <cleger@rivosinc.com> Co-developed-by: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com> Signed-off-by: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
This module, once loaded, will execute a series of tests using the SSE
framework. The provided script will check for any error reported by the
test module.
Add stress={0,1,2} modes so the same module can cover repeated handler
entry, SBI calls from a handler, PMU activity and re-injection. Also make
the tests tolerate events that are already registered, and keep the
attribute read buffer lifetime local to the SBI call.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Co-developed-by: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com>
Signed-off-by: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v9,1/5] riscv: add SBI SSE extension definitions" |
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Patch 1: "[v9,1/5] riscv: add SBI SSE extension definitions" |
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Patch 1: "[v9,1/5] riscv: add SBI SSE extension definitions" |
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Patch 1: "[v9,1/5] riscv: add SBI SSE extension definitions" |
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Patch 1: "[v9,1/5] riscv: add SBI SSE extension definitions" |
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Patch 1: "[v9,1/5] riscv: add SBI SSE extension definitions" |
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Patch 1: "[v9,1/5] riscv: add SBI SSE extension definitions" |
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Patch 1: "[v9,1/5] riscv: add SBI SSE extension definitions" |
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Patch 1: "[v9,1/5] riscv: add SBI SSE extension definitions" |
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Patch 1: "[v9,1/5] riscv: add SBI SSE extension definitions" |
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Patch 1: "[v9,1/5] riscv: add SBI SSE extension definitions" |
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Patch 1: "[v9,1/5] riscv: add SBI SSE extension definitions" |
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Patch 2: "[v9,2/5] riscv: add support for SBI Supervisor Software Events extension" |
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Patch 2: "[v9,2/5] riscv: add support for SBI Supervisor Software Events extension" |
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Patch 2: "[v9,2/5] riscv: add support for SBI Supervisor Software Events extension" |
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Patch 2: "[v9,2/5] riscv: add support for SBI Supervisor Software Events extension" |
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Patch 2: "[v9,2/5] riscv: add support for SBI Supervisor Software Events extension" |
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Patch 2: "[v9,2/5] riscv: add support for SBI Supervisor Software Events extension" |
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Patch 2: "[v9,2/5] riscv: add support for SBI Supervisor Software Events extension" |
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Patch 2: "[v9,2/5] riscv: add support for SBI Supervisor Software Events extension" |
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Patch 2: "[v9,2/5] riscv: add support for SBI Supervisor Software Events extension" |
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Patch 2: "[v9,2/5] riscv: add support for SBI Supervisor Software Events extension" |
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Patch 2: "[v9,2/5] riscv: add support for SBI Supervisor Software Events extension" |
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Patch 2: "[v9,2/5] riscv: add support for SBI Supervisor Software Events extension" |
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Patch 3: "[v9,3/5] drivers: firmware: add riscv SSE support" |
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Patch 3: "[v9,3/5] drivers: firmware: add riscv SSE support" |
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Patch 4: "[v9,4/5] perf: RISC-V: add support for SSE event" |
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Patch 4: "[v9,4/5] perf: RISC-V: add support for SSE event" |
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Patch 4: "[v9,4/5] perf: RISC-V: add support for SSE event" |
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Patch 4: "[v9,4/5] perf: RISC-V: add support for SSE event" |
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Patch 4: "[v9,4/5] perf: RISC-V: add support for SSE event" |
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Patch 4: "[v9,4/5] perf: RISC-V: add support for SSE event" |
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Patch 4: "[v9,4/5] perf: RISC-V: add support for SSE event" |
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Patch 4: "[v9,4/5] perf: RISC-V: add support for SSE event" |
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Patch 4: "[v9,4/5] perf: RISC-V: add support for SSE event" |
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Patch 4: "[v9,4/5] perf: RISC-V: add support for SSE event" |
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Patch 4: "[v9,4/5] perf: RISC-V: add support for SSE event" |
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Patch 4: "[v9,4/5] perf: RISC-V: add support for SSE event" |
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Patch 5: "[v9,5/5] selftests/riscv: add SSE test module" |
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Patch 5: "[v9,5/5] selftests/riscv: add SSE test module" |
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Patch 5: "[v9,5/5] selftests/riscv: add SSE test module" |
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Patch 5: "[v9,5/5] selftests/riscv: add SSE test module" |
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Patch 5: "[v9,5/5] selftests/riscv: add SSE test module" |
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Patch 5: "[v9,5/5] selftests/riscv: add SSE test module" |
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Patch 5: "[v9,5/5] selftests/riscv: add SSE test module" |
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Patch 5: "[v9,5/5] selftests/riscv: add SSE test module" |
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Patch 5: "[v9,5/5] selftests/riscv: add SSE test module" |
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Patch 5: "[v9,5/5] selftests/riscv: add SSE test module" |
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Patch 5: "[v9,5/5] selftests/riscv: add SSE test module" |
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Patch 5: "[v9,5/5] selftests/riscv: add SSE test module" |
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PR for series 1092025 applied to workflow__riscv__fixes
Name: riscv: add SBI Supervisor Software Events support
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1092025
Version: 9