[PW_SID:1092813] riscv: hwprobe: Expose RVA23U64 base behavior#1909
[PW_SID:1092813] riscv: hwprobe: Expose RVA23U64 base behavior#1909linux-riscv-bot wants to merge 10 commits into
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Commit 30c3099 ("riscv/hwprobe: add zicfilp / zicfiss enumeration in hwprobe") added RISCV_HWPROBE_EXT_ZICFISS as bit 0 of RISCV_HWPROBE_KEY_IMA_EXT_1 but did not add a matching entry to Documentation/arch/riscv/hwprobe.rst. Add it now. Fixes: 30c3099 ("riscv/hwprobe: add zicfilp / zicfiss enumeration in hwprobe") Signed-off-by: Guodong Xu <guodong@riscstar.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
A handful of vendor-extension entries indent continuation lines with a tab character, while the rest of hwprobe.rst uses spaces. Replace those tabs with spaces so the file is consistently space-indented. Cosmetic update, no functional change. Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The base extensions are often lowercase and were written as lowercase in hwcap, but other references to these extensions in the kernel are uppercase. Standardize the case to make it easier to handle macro expansion. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> [Apply KVM_ISA_EXT_ARR(), fixup all KVM use.] Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Zicclsm requires misaligned support for all regular load and store instructions, both scalar and vector, but not AMOs or other specialized forms of memory access, to main memory regions with both the cacheability and coherence PMAs, as defined in the profiles spec. Even though mandated, misaligned loads and stores might execute extremely slowly. Standard software distributions should assume their existence only for correctness, not for performance. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Charlie Jenkins <charlie@rivosinc.com> Signed-off-by: Jesse Taube <jesse@rivosinc.com> [Rebased, rewrote doc text, minor commit message revisions] Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
…probe
Add Ziccamoa, Ziccif, and Za64rs to riscv_isa_ext[] so they can be
parsed from devicetree/ACPI ISA strings. Ziccrse is already present
in cpufeature; this patch only adds its hwprobe exposure.
Expose all four extensions via hwprobe through new bits in
RISCV_HWPROBE_KEY_IMA_EXT_1 (RISCV_HWPROBE_EXT_ZICCAMOA, _ZICCIF,
_ZICCRSE, _ZA64RS), so userspace can probe each of these
RVA23U64-mandatory extensions individually.
Rationale for the validation dependencies added for Ziccamoa and Za64rs:
1) Ziccamoa depends on Zaamo. The RVA23 profile prose was updated
post-ratification to spell out the Zaamo reference: commit
2b218613752d in riscv/riscv-profiles ("Improve description of
Ziccamoa (#224)") reworded the rva23-profile.adoc (and other profiles
that include Ziccamoa) text from "must support all atomics in A" to
"must support all atomics in the Zaamo extension" [1].
2) Za64rs depends on Zalrsc. The unprivileged ISA manual src/zars.adoc,
integrated in commit ebe06adc22cd ("Integrate profiles as Volume III
(#2771)"), defines Za64rs as: "The Za64rs extension requires that the
reservation sets used by the instructions in the Zalrsc extension be
contiguous, naturally aligned, and at most 64 bytes in size" [2].
Link: riscv/riscv-profiles@2b21861 [1]
Link: https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/zars.adoc [2]
Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add B to hwcap and ensure when B is present that Zba, Zbb, and Zbs are all set. Also expose B via hwprobe (RISCV_HWPROBE_EXT_B in RISCV_HWPROBE_KEY_IMA_EXT_1) so that userspace can probe B directly, mirroring the F/D/C/V pattern where each is reported via both hwcap and hwprobe. Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> [Add B to hwprobe] Signed-off-by: Guodong Xu <guodong@riscstar.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Querying whether a given user PMLEN is supported is needed for RVA23U64 base detection from outside arch/riscv/kernel/process.c. Add riscv_have_user_pmlen() to expose this. Link: https://lore.kernel.org/linux-riscv/rfuwa7a3ebe76udmnwyrssjy7shkkgxntvhwzn6oquysj4tuyp@xzvpylcfhz53/ Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> [Guodong: replace exported booleans with getter per Andrew's suggestion] Signed-off-by: Guodong Xu <guodong@riscstar.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Introduce a per-hart and host-wide bitmap of conformant ISA "bases" -- named profile-class sets such as IMA and RVA23U64 -- and compute both at init time. This is the cache that subsequent consumers (hwprobe's RVA23U64 base behavior bit, /proc/cpuinfo's "isa bases" lines, etc.) read without recomputing. riscv_init_isa_bases() iterates over all possible cpus to populate each hart_isa[cpu].isa_bases, then computes the host-wide riscv_isa_bases against the AND-across-harts riscv_isa bitmap. It is registered as a subsys_initcall so it executes after core_initcall(tagged_addr_init), which probes senvcfg.PMM and populates have_user_pmlen_*. Without that ordering, riscv_have_user_pmlen(7) would still return its default false and the RVA23U64 detection path would always bail. The detection itself is encapsulated in riscv_set_isa_bases(), which takes an output bases bitmap and an input ISA bitmap. Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Output two new lines per processor in /proc/cpuinfo: isa bases : <bases that all harts conform to> hart isa bases : <bases that this specific hart conforms to> These read directly from the cached riscv_isa_bases and hart_isa[cpu].isa_bases bitmaps populated at boot by riscv_init_isa_bases(). Example output on qemu booted with -cpu rva23s64,sv39=on,pmp=on (showing only the new lines plus their neighbors for context): processor : 0 hart : 4 isa bases : rv64ima rva23u64 isa : rv64imafdcbvh_zicbom_zicbop_... mmu : sv39 ... mimpid : 0x0 hart isa bases : rv64ima rva23u64 hart isa : rv64imafdcbvh_zicbom_zicbop_... Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Provide a hwprobe base-behavior bit so userspace can check RVA23U64 support in one call. Without it, a consumer needs five hwprobe calls and four prctl calls, which is error-prone to require of every caller. Most software treats RVA23U64 as a new base anyway, so expose it directly. Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v2,01/10] riscv: hwprobe.rst: Document EXT_ZICFISS" |
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Patch 1: "[v2,01/10] riscv: hwprobe.rst: Document EXT_ZICFISS" |
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Patch 1: "[v2,01/10] riscv: hwprobe.rst: Document EXT_ZICFISS" |
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Patch 1: "[v2,01/10] riscv: hwprobe.rst: Document EXT_ZICFISS" |
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Patch 1: "[v2,01/10] riscv: hwprobe.rst: Document EXT_ZICFISS" |
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Patch 1: "[v2,01/10] riscv: hwprobe.rst: Document EXT_ZICFISS" |
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Patch 1: "[v2,01/10] riscv: hwprobe.rst: Document EXT_ZICFISS" |
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Patch 1: "[v2,01/10] riscv: hwprobe.rst: Document EXT_ZICFISS" |
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Patch 1: "[v2,01/10] riscv: hwprobe.rst: Document EXT_ZICFISS" |
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Patch 1: "[v2,01/10] riscv: hwprobe.rst: Document EXT_ZICFISS" |
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Patch 1: "[v2,01/10] riscv: hwprobe.rst: Document EXT_ZICFISS" |
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Patch 1: "[v2,01/10] riscv: hwprobe.rst: Document EXT_ZICFISS" |
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Patch 2: "[v2,02/10] riscv: hwprobe.rst: Replace tabs with spaces" |
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Patch 2: "[v2,02/10] riscv: hwprobe.rst: Replace tabs with spaces" |
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Patch 2: "[v2,02/10] riscv: hwprobe.rst: Replace tabs with spaces" |
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Patch 2: "[v2,02/10] riscv: hwprobe.rst: Replace tabs with spaces" |
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Patch 2: "[v2,02/10] riscv: hwprobe.rst: Replace tabs with spaces" |
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Patch 2: "[v2,02/10] riscv: hwprobe.rst: Replace tabs with spaces" |
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Patch 2: "[v2,02/10] riscv: hwprobe.rst: Replace tabs with spaces" |
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Patch 2: "[v2,02/10] riscv: hwprobe.rst: Replace tabs with spaces" |
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Patch 8: "[v2,08/10] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection" |
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Patch 8: "[v2,08/10] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection" |
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Patch 8: "[v2,08/10] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection" |
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Patch 8: "[v2,08/10] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection" |
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Patch 9: "[v2,09/10] riscv: cpu: Output isa bases lines in cpuinfo" |
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Patch 9: "[v2,09/10] riscv: cpu: Output isa bases lines in cpuinfo" |
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Patch 9: "[v2,09/10] riscv: cpu: Output isa bases lines in cpuinfo" |
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Patch 9: "[v2,09/10] riscv: cpu: Output isa bases lines in cpuinfo" |
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Patch 9: "[v2,09/10] riscv: cpu: Output isa bases lines in cpuinfo" |
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Patch 9: "[v2,09/10] riscv: cpu: Output isa bases lines in cpuinfo" |
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Patch 9: "[v2,09/10] riscv: cpu: Output isa bases lines in cpuinfo" |
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Patch 9: "[v2,09/10] riscv: cpu: Output isa bases lines in cpuinfo" |
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Patch 9: "[v2,09/10] riscv: cpu: Output isa bases lines in cpuinfo" |
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Patch 9: "[v2,09/10] riscv: cpu: Output isa bases lines in cpuinfo" |
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Patch 9: "[v2,09/10] riscv: cpu: Output isa bases lines in cpuinfo" |
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Patch 9: "[v2,09/10] riscv: cpu: Output isa bases lines in cpuinfo" |
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Patch 10: "[v2,10/10] riscv: hwprobe: Introduce rva23u64 base behavior" |
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Patch 10: "[v2,10/10] riscv: hwprobe: Introduce rva23u64 base behavior" |
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Patch 10: "[v2,10/10] riscv: hwprobe: Introduce rva23u64 base behavior" |
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Patch 10: "[v2,10/10] riscv: hwprobe: Introduce rva23u64 base behavior" |
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Patch 10: "[v2,10/10] riscv: hwprobe: Introduce rva23u64 base behavior" |
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Patch 10: "[v2,10/10] riscv: hwprobe: Introduce rva23u64 base behavior" |
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Patch 10: "[v2,10/10] riscv: hwprobe: Introduce rva23u64 base behavior" |
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Patch 10: "[v2,10/10] riscv: hwprobe: Introduce rva23u64 base behavior" |
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Patch 10: "[v2,10/10] riscv: hwprobe: Introduce rva23u64 base behavior" |
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Patch 10: "[v2,10/10] riscv: hwprobe: Introduce rva23u64 base behavior" |
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Patch 10: "[v2,10/10] riscv: hwprobe: Introduce rva23u64 base behavior" |
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Patch 10: "[v2,10/10] riscv: hwprobe: Introduce rva23u64 base behavior" |
5 participants
PR for series 1092813 applied to workflow__riscv__for-next
Name: riscv: hwprobe: Expose RVA23U64 base behavior
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1092813
Version: 2