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[PW_SID:1095143] Add OpenCores PTC PWM support #1944

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[PW_SID:1095143] Add OpenCores PTC PWM support #1944

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4bb65fe
dt-bindings: pwm: opencores: Drop starfive compatibles and update mai…
hal-feng May 15, 2026
95da73e
riscv: dts: starfive: Correct pwm nodes
hal-feng May 15, 2026
f1a9c80
pwm: Add OpenCores PTC PWM driver
hal-feng May 15, 2026
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10 changes: 3 additions & 7 deletions Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: OpenCores PWM controller

maintainers:
- William Qiu <william.qiu@starfivetech.com>
- Hal Feng <hal.feng@starfivetech.com>

description:
The OpenCores PTC ip core contains a PWM controller. When operating in PWM
Expand All @@ -20,10 +20,6 @@ allOf:
properties:
compatible:
items:
- enum:
- starfive,jh7100-pwm
- starfive,jh7110-pwm
- starfive,jh8100-pwm
- const: opencores,pwm-v1

reg:
Expand All @@ -48,8 +44,8 @@ additionalProperties: false
examples:
- |
pwm@12490000 {
compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
reg = <0x12490000 0x10000>;
compatible = "opencores,pwm-v1";
reg = <0x12490000 0x10>;
clocks = <&clkgen 181>;
resets = <&rstgen 109>;
#pwm-cells = <3>;
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6 changes: 6 additions & 0 deletions MAINTAINERS
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Expand Up @@ -19984,6 +19984,12 @@ F: Documentation/i2c/busses/i2c-ocores.rst
F: drivers/i2c/busses/i2c-ocores.c
F: include/linux/platform_data/i2c-ocores.h

OPENCORES PWM DRIVER
M: Hal Feng <hal.feng@starfivetech.com>
S: Supported
F: Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
F: drivers/pwm/pwm-ocores.c

OPENRISC ARCHITECTURE
M: Jonas Bonn <jonas@southpole.se>
M: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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28 changes: 22 additions & 6 deletions arch/riscv/boot/dts/starfive/jh7100-common.dtsi
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Expand Up @@ -199,13 +199,23 @@
};
};

pwm_pins: pwm-0 {
pwm-pins {
pwm0_pins: pwm0-0 {
pwm0-pins {
pinmux = <GPIOMUX(7,
GPO_PWM_PAD_OUT_BIT0,
GPO_PWM_PAD_OE_N_BIT0,
GPI_NONE)>,
<GPIOMUX(5,
GPI_NONE)>;
bias-disable;
drive-strength = <35>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};

pwm1_pins: pwm1-0 {
pwm1-pins {
pinmux = <GPIOMUX(5,
GPO_PWM_PAD_OUT_BIT1,
GPO_PWM_PAD_OE_N_BIT1,
GPI_NONE)>;
Expand Down Expand Up @@ -359,9 +369,15 @@
clock-frequency = <27000000>;
};

&pwm {
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pins>;
status = "okay";
};

&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
pinctrl-0 = <&pwm1_pins>;
status = "okay";
};

Expand Down
69 changes: 66 additions & 3 deletions arch/riscv/boot/dts/starfive/jh7100.dtsi
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Expand Up @@ -360,9 +360,72 @@
<&rstgen JH7100_RSTN_WDT>;
};

pwm: pwm@12490000 {
compatible = "starfive,jh7100-pwm", "opencores,pwm-v1";
reg = <0x0 0x12490000 0x0 0x10000>;
pwm0: pwm@12490000 {
compatible = "opencores,pwm-v1";
reg = <0x0 0x12490000 0x0 0x10>;
clocks = <&clkgen JH7100_CLK_PWM_APB>;
resets = <&rstgen JH7100_RSTN_PWM_APB>;
#pwm-cells = <3>;
status = "disabled";
};

pwm1: pwm@12490010 {
compatible = "opencores,pwm-v1";
reg = <0x0 0x12490010 0x0 0x10>;
clocks = <&clkgen JH7100_CLK_PWM_APB>;
resets = <&rstgen JH7100_RSTN_PWM_APB>;
#pwm-cells = <3>;
status = "disabled";
};

pwm2: pwm@12490020 {
compatible = "opencores,pwm-v1";
reg = <0x0 0x12490020 0x0 0x10>;
clocks = <&clkgen JH7100_CLK_PWM_APB>;
resets = <&rstgen JH7100_RSTN_PWM_APB>;
#pwm-cells = <3>;
status = "disabled";
};

pwm3: pwm@12490030 {
compatible = "opencores,pwm-v1";
reg = <0x0 0x12490030 0x0 0x10>;
clocks = <&clkgen JH7100_CLK_PWM_APB>;
resets = <&rstgen JH7100_RSTN_PWM_APB>;
#pwm-cells = <3>;
status = "disabled";
};

pwm4: pwm@12498000 {
compatible = "opencores,pwm-v1";
reg = <0x0 0x12498000 0x0 0x10>;
clocks = <&clkgen JH7100_CLK_PWM_APB>;
resets = <&rstgen JH7100_RSTN_PWM_APB>;
#pwm-cells = <3>;
status = "disabled";
};

pwm5: pwm@12498010 {
compatible = "opencores,pwm-v1";
reg = <0x0 0x12498010 0x0 0x10>;
clocks = <&clkgen JH7100_CLK_PWM_APB>;
resets = <&rstgen JH7100_RSTN_PWM_APB>;
#pwm-cells = <3>;
status = "disabled";
};

pwm6: pwm@12498020 {
compatible = "opencores,pwm-v1";
reg = <0x0 0x12498020 0x0 0x10>;
clocks = <&clkgen JH7100_CLK_PWM_APB>;
resets = <&rstgen JH7100_RSTN_PWM_APB>;
#pwm-cells = <3>;
status = "disabled";
};

pwm7: pwm@12498030 {
compatible = "opencores,pwm-v1";
reg = <0x0 0x12498030 0x0 0x10>;
clocks = <&clkgen JH7100_CLK_PWM_APB>;
resets = <&rstgen JH7100_RSTN_PWM_APB>;
#pwm-cells = <3>;
Expand Down
27 changes: 21 additions & 6 deletions arch/riscv/boot/dts/starfive/jh7110-common.dtsi
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Expand Up @@ -351,9 +351,14 @@
};
};

&pwm {
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
pinctrl-0 = <&pwm0_pins>;
};

&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pins>;
};

&spi0 {
Expand Down Expand Up @@ -553,12 +558,22 @@
};
};

pwm_pins: pwm-0 {
pwm-pins {
pwm0_pins: pwm0-0 {
pwm0-pins {
pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
GPOEN_SYS_PWM0_CHANNEL0,
GPI_NONE)>,
<GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
GPI_NONE)>;
bias-disable;
drive-strength = <12>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};

pwm1_pins: pwm1-0 {
pwm1-pins {
pinmux = <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
GPOEN_SYS_PWM0_CHANNEL1,
GPI_NONE)>;
bias-disable;
Expand Down
6 changes: 5 additions & 1 deletion arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
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Expand Up @@ -68,7 +68,11 @@
motorcomm,tx-clk-adj-enabled;
};

&pwm {
&pwm0 {
status = "okay";
};

&pwm1 {
status = "okay";
};

Expand Down
6 changes: 5 additions & 1 deletion arch/riscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi
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Expand Up @@ -87,7 +87,11 @@
motorcomm,tx-clk-adj-enabled;
};

&pwm {
&pwm0 {
status = "okay";
};

&pwm1 {
status = "okay";
};

Expand Down
6 changes: 5 additions & 1 deletion arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
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Expand Up @@ -95,7 +95,11 @@
motorcomm,tx-clk-100-inverted;
};

&pwm {
&pwm0 {
status = "okay";
};

&pwm1 {
status = "okay";
};

Expand Down
6 changes: 5 additions & 1 deletion arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
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Expand Up @@ -74,7 +74,11 @@
tx-internal-delay-ps = <1500>;
};

&pwm {
&pwm0 {
status = "okay";
};

&pwm1 {
status = "okay";
};

Expand Down
6 changes: 5 additions & 1 deletion arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
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Expand Up @@ -73,7 +73,11 @@
status = "okay";
};

&pwm {
&pwm0 {
status = "okay";
};

&pwm1 {
status = "okay";
};

Expand Down
69 changes: 66 additions & 3 deletions arch/riscv/boot/dts/starfive/jh7110.dtsi
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Expand Up @@ -846,9 +846,72 @@
status = "disabled";
};

pwm: pwm@120d0000 {
compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
reg = <0x0 0x120d0000 0x0 0x10000>;
pwm0: pwm@120d0000 {
compatible = "opencores,pwm-v1";
reg = <0x0 0x120d0000 0x0 0x10>;
clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
resets = <&syscrg JH7110_SYSRST_PWM_APB>;
#pwm-cells = <3>;
status = "disabled";
};

pwm1: pwm@120d0010 {
compatible = "opencores,pwm-v1";
reg = <0x0 0x120d0010 0x0 0x10>;
clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
resets = <&syscrg JH7110_SYSRST_PWM_APB>;
#pwm-cells = <3>;
status = "disabled";
};

pwm2: pwm@120d0020 {
compatible = "opencores,pwm-v1";
reg = <0x0 0x120d0020 0x0 0x10>;
clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
resets = <&syscrg JH7110_SYSRST_PWM_APB>;
#pwm-cells = <3>;
status = "disabled";
};

pwm3: pwm@120d0030 {
compatible = "opencores,pwm-v1";
reg = <0x0 0x120d0030 0x0 0x10>;
clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
resets = <&syscrg JH7110_SYSRST_PWM_APB>;
#pwm-cells = <3>;
status = "disabled";
};

pwm4: pwm@120d8000 {
compatible = "opencores,pwm-v1";
reg = <0x0 0x120d8000 0x0 0x10>;
clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
resets = <&syscrg JH7110_SYSRST_PWM_APB>;
#pwm-cells = <3>;
status = "disabled";
};

pwm5: pwm@120d8010 {
compatible = "opencores,pwm-v1";
reg = <0x0 0x120d8010 0x0 0x10>;
clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
resets = <&syscrg JH7110_SYSRST_PWM_APB>;
#pwm-cells = <3>;
status = "disabled";
};

pwm6: pwm@120d8020 {
compatible = "opencores,pwm-v1";
reg = <0x0 0x120d8020 0x0 0x10>;
clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
resets = <&syscrg JH7110_SYSRST_PWM_APB>;
#pwm-cells = <3>;
status = "disabled";
};

pwm7: pwm@120d8030 {
compatible = "opencores,pwm-v1";
reg = <0x0 0x120d8030 0x0 0x10>;
clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
resets = <&syscrg JH7110_SYSRST_PWM_APB>;
#pwm-cells = <3>;
Expand Down
12 changes: 12 additions & 0 deletions drivers/pwm/Kconfig
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Expand Up @@ -534,6 +534,18 @@ config PWM_NTXEC
controller found in certain e-book readers designed by the original
design manufacturer Netronix.

config PWM_OCORES
tristate "OpenCores PTC PWM support"
depends on HAS_IOMEM && OF
depends on COMMON_CLK
depends on ARCH_STARFIVE || COMPILE_TEST
help
PWM driver for OpenCores PTC IP core.
For details see https://opencores.org/projects/ptc.

To compile this driver as a module, choose M here: the module
will be called pwm-ocores.

config PWM_OMAP_DMTIMER
tristate "OMAP Dual-Mode Timer PWM support"
depends on OF
Expand Down
1 change: 1 addition & 0 deletions drivers/pwm/Makefile
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Expand Up @@ -47,6 +47,7 @@ obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o
obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o
obj-$(CONFIG_PWM_OCORES) += pwm-ocores.o
obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o
obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o
obj-$(CONFIG_PWM_PXA) += pwm-pxa.o
Expand Down
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