[PW_SID:1096361] riscv: Introduce support for hardware break/watchpoints by linux-riscv-bot · Pull Request #1961 · linux-riscv/linux

linux-riscv-bot · 2026-05-18T11:06:59Z

PR for series 1096361 applied to workflow__riscv__fixes

Name: riscv: Introduce support for hardware break/watchpoints
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1096361
Version: 4

RISC-V hardware breakpoint framework is built on top of perf subsystem and uses SBI debug trigger extension to install/uninstall/update/enable/disable hardware triggers as specified in Sdtrig ISA extension. Signed-off-by: Himanshu Chauhan <himanshu.chauhan@oss.qualcomm.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Add self test for riscv architecture. It uses ptrace to ptrace framework to set/unset break/watchpoint and uses signals to check triggers. Signed-off-by: Himanshu Chauhan <himanshu.chauhan@oss.qualcomm.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

linux-riscv-bot · 2026-05-18T11:12:41Z

Patch 1: "[v4,1/2] riscv: Introduce support for hardware break/watchpoints"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 124.00 seconds
Result: ERROR
Output:

Full log:
W: Support for running offline not available (unshare: unshare failed: Operation not permitted)
tuxmake --download-all-korg-gcc-toolchains --target-arch=riscv --kconfig=rv32_defconfig --toolchain=llvm --wrapper=ccache --environment=KBUILD_BUILD_TIMESTAMP=@1621270510 --environment=KBUILD_BUILD_USER=tuxmake --environment=KBUILD_BUILD_HOST=tuxmake --environment=KCFLAGS=-ffile-prefix-map=/build/tmp.NNtbPQJWy6/build/= --runtime=null --image=docker.io/tuxmake/riscv_clang CROSS_COMPILE=riscv64-linux- config default kernel xipkernel modules dtbs dtbs-legacy debugkernel headers
make --silent --keep-going --jobs=48 O=/build/tmp.NNtbPQJWy6/build ARCH=riscv CROSS_COMPILE=riscv64-linux- LLVM=1 'CC=ccache clang' 'HOSTCC=ccache clang' rv32_defconfig
make --silent --keep-going --jobs=48 O=/build/tmp.NNtbPQJWy6/build ARCH=riscv CROSS_COMPILE=riscv64-linux- LLVM=1 'CC=ccache clang' 'HOSTCC=ccache clang'
/build/tmpshhsjat6/arch/riscv/kernel/hw_breakpoint.c:245:16: error: use of undeclared identifier 'RISCV_DBTR_MCSIZEHI_BIT_MASK'; did you mean 'RISCV_DBTR_MCSIZELO_BIT_MASK'?
  245 |                 hw->tdata1 = RISCV_DBTR_SET_MC_SIZEHI(hw->tdata1, 0);
      |                              ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:247:14: note: expanded from macro 'RISCV_DBTR_SET_MC_SIZEHI'
  247 |                 mcsht1 &= ~RISCV_DBTR_BIT_MASK(MC, SIZEHI);             \
      |                            ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:32:2: note: expanded from macro 'RISCV_DBTR_BIT_MASK'
   32 |         RISCV_DBTR_##_prefix##_name##_BIT_MASK
      |         ^
<scratch space>:104:1: note: expanded from here
  104 | RISCV_DBTR_MCSIZEHI_BIT_MASK
      | ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:127:2: note: 'RISCV_DBTR_MCSIZELO_BIT_MASK' declared here
  127 |         RISCV_DBTR_BIT_MASK(MC, SIZELO) = RISCV_DBTR_BIT_MASK_VAL(MC, SIZELO, 2),
      |         ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:32:2: note: expanded from macro 'RISCV_DBTR_BIT_MASK'
   32 |         RISCV_DBTR_##_prefix##_name##_BIT_MASK
      |         ^
<scratch space>:61:1: note: expanded from here
   61 | RISCV_DBTR_MCSIZELO_BIT_MASK
      | ^
/build/tmpshhsjat6/arch/riscv/kernel/hw_breakpoint.c:245:16: error: use of undeclared identifier 'RISCV_DBTR_MC_SIZEHI_BIT'; did you mean 'RISCV_DBTR_MC_SIZELO_BIT'?
  245 |                 hw->tdata1 = RISCV_DBTR_SET_MC_SIZEHI(hw->tdata1, 0);
      |                              ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:248:25: note: expanded from macro 'RISCV_DBTR_SET_MC_SIZEHI'
  248 |                 mcsht1 |= (((_val) << RISCV_DBTR_BIT(MC, SIZEHI))       \
      |                                       ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:29:2: note: expanded from macro 'RISCV_DBTR_BIT'
   29 |         RISCV_DBTR_##_prefix##_##_name##_BIT
      |         ^
<scratch space>:108:1: note: expanded from here
  108 | RISCV_DBTR_MC_SIZEHI_BIT
      | ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:96:2: note: 'RISCV_DBTR_MC_SIZELO_BIT' declared here
   96 |         RISCV_DBTR_BIT(MC, SIZELO)   = 16,
      |         ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:29:2: note: expanded from macro 'RISCV_DBTR_BIT'
   29 |         RISCV_DBTR_##_prefix##_##_name##_BIT
      |         ^
<scratch space>:166:1: note: expanded from here
  166 | RISCV_DBTR_MC_SIZELO_BIT
      | ^
/build/tmpshhsjat6/arch/riscv/kernel/hw_breakpoint.c:245:16: error: use of undeclared identifier 'RISCV_DBTR_MCSIZEHI_BIT_MASK'; did you mean 'RISCV_DBTR_MCSIZELO_BIT_MASK'?
  245 |                 hw->tdata1 = RISCV_DBTR_SET_MC_SIZEHI(hw->tdata1, 0);
      |                              ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:249:9: note: expanded from macro 'RISCV_DBTR_SET_MC_SIZEHI'
  249 |                            & RISCV_DBTR_BIT_MASK(MC, SIZEHI));          \
      |                              ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:32:2: note: expanded from macro 'RISCV_DBTR_BIT_MASK'
   32 |         RISCV_DBTR_##_prefix##_name##_BIT_MASK
      |         ^
<scratch space>:111:1: note: expanded from here
  111 | RISCV_DBTR_MCSIZEHI_BIT_MASK
      | ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:127:2: note: 'RISCV_DBTR_MCSIZELO_BIT_MASK' declared here
  127 |         RISCV_DBTR_BIT_MASK(MC, SIZELO) = RISCV_DBTR_BIT_MASK_VAL(MC, SIZELO, 2),
      |         ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:32:2: note: expanded from macro 'RISCV_DBTR_BIT_MASK'
   32 |         RISCV_DBTR_##_prefix##_name##_BIT_MASK
      |         ^
<scratch space>:61:1: note: expanded from here
   61 | RISCV_DBTR_MCSIZELO_BIT_MASK
      | ^
/build/tmpshhsjat6/arch/riscv/kernel/hw_breakpoint.c:271:17: error: use of undeclared identifier 'RISCV_DBTR_MCSIZEHI_BIT_MASK'; did you mean 'RISCV_DBTR_MCSIZELO_BIT_MASK'?
  271 |                         hw->tdata1 = RISCV_DBTR_SET_MC_SIZEHI(hw->tdata1, 0);
      |                                      ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:247:14: note: expanded from macro 'RISCV_DBTR_SET_MC_SIZEHI'
  247 |                 mcsht1 &= ~RISCV_DBTR_BIT_MASK(MC, SIZEHI);             \
      |                            ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:32:2: note: expanded from macro 'RISCV_DBTR_BIT_MASK'
   32 |         RISCV_DBTR_##_prefix##_name##_BIT_MASK
      |         ^
<scratch space>:154:1: note: expanded from here
  154 | RISCV_DBTR_MCSIZEHI_BIT_MASK
      | ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:127:2: note: 'RISCV_DBTR_MCSIZELO_BIT_MASK' declared here
  127 |         RISCV_DBTR_BIT_MASK(MC, SIZELO) = RISCV_DBTR_BIT_MASK_VAL(MC, SIZELO, 2),
      |         ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:32:2: note: expanded from macro 'RISCV_DBTR_BIT_MASK'
   32 |         RISCV_DBTR_##_prefix##_name##_BIT_MASK
      |         ^
<scratch space>:61:1: note: expanded from here
   61 | RISCV_DBTR_MCSIZELO_BIT_MASK
      | ^
/build/tmpshhsjat6/arch/riscv/kernel/hw_breakpoint.c:271:17: error: use of undeclared identifier 'RISCV_DBTR_MC_SIZEHI_BIT'; did you mean 'RISCV_DBTR_MC_SIZELO_BIT'?
  271 |                         hw->tdata1 = RISCV_DBTR_SET_MC_SIZEHI(hw->tdata1, 0);
      |                                      ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:248:25: note: expanded from macro 'RISCV_DBTR_SET_MC_SIZEHI'
  248 |                 mcsht1 |= (((_val) << RISCV_DBTR_BIT(MC, SIZEHI))       \
      |                                       ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:29:2: note: expanded from macro 'RISCV_DBTR_BIT'
   29 |         RISCV_DBTR_##_prefix##_##_name##_BIT
      |         ^
<scratch space>:158:1: note: expanded from here
  158 | RISCV_DBTR_MC_SIZEHI_BIT
      | ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:96:2: note: 'RISCV_DBTR_MC_SIZELO_BIT' declared here
   96 |         RISCV_DBTR_BIT(MC, SIZELO)   = 16,
      |         ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:29:2: note: expanded from macro 'RISCV_DBTR_BIT'
   29 |         RISCV_DBTR_##_prefix##_##_name##_BIT
      |         ^
<scratch space>:166:1: note: expanded from here
  166 | RISCV_DBTR_MC_SIZELO_BIT
      | ^
/build/tmpshhsjat6/arch/riscv/kernel/hw_breakpoint.c:271:17: error: use of undeclared identifier 'RISCV_DBTR_MCSIZEHI_BIT_MASK'; did you mean 'RISCV_DBTR_MCSIZELO_BIT_MASK'?
  271 |                         hw->tdata1 = RISCV_DBTR_SET_MC_SIZEHI(hw->tdata1, 0);
      |                                      ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:249:9: note: expanded from macro 'RISCV_DBTR_SET_MC_SIZEHI'
  249 |                            & RISCV_DBTR_BIT_MASK(MC, SIZEHI));          \
      |                              ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:32:2: note: expanded from macro 'RISCV_DBTR_BIT_MASK'
   32 |         RISCV_DBTR_##_prefix##_name##_BIT_MASK
      |         ^
<scratch space>:161:1: note: expanded from here
  161 | RISCV_DBTR_MCSIZEHI_BIT_MASK
      | ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:127:2: note: 'RISCV_DBTR_MCSIZELO_BIT_MASK' declared here
I: config: PASS in 0:00:33.140482
I: default: FAIL in 0:01:23.579739
I: kernel: SKIP in 0:00:00.000007
I: xipkernel: SKIP in 0:00:00.000002
I: modules: FAIL in 0:00:00.099484
I: dtbs: PASS in 0:00:01.784469
I: dtbs-legacy: SKIP in 0:00:00.005070
I: debugkernel: SKIP in 0:00:00.000005
I: headers: PASS in 0:00:01.086578
I: build output in /build/tmp.NNtbPQJWy6
  127 |         RISCV_DBTR_BIT_MASK(MC, SIZELO) = RISCV_DBTR_BIT_MASK_VAL(MC, SIZELO, 2),
      |         ^
/build/tmpshhsjat6/arch/riscv/include/asm/hw_breakpoint.h:32:2: note: expanded from macro 'RISCV_DBTR_BIT_MASK'
   32 |         RISCV_DBTR_##_prefix##_name##_BIT_MASK
      |         ^
<scratch space>:61:1: note: expanded from here
   61 | RISCV_DBTR_MCSIZELO_BIT_MASK
      | ^
6 errors generated.
make[5]: *** [/build/tmpshhsjat6/scripts/Makefile.build:289: arch/riscv/kernel/hw_breakpoint.o] Error 1
make[5]: Target 'arch/riscv/kernel/' not remade because of errors.
make[4]: *** [/build/tmpshhsjat6/scripts/Makefile.build:548: arch/riscv/kernel] Error 2
make[4]: Target 'arch/riscv/' not remade because of errors.
make[3]: *** [/build/tmpshhsjat6/scripts/Makefile.build:548: arch/riscv] Error 2
make[3]: Target './' not remade because of errors.
make[2]: *** [/build/tmpshhsjat6/Makefile:2141: .] Error 2
make[2]: Target '__all' not remade because of errors.
make[1]: *** [/build/tmpshhsjat6/Makefile:248: __sub-make] Error 2
make[1]: Target '__all' not remade because of errors.
make: *** [Makefile:248: __sub-make] Error 2
make: Target '__all' not remade because of errors.
rm -rf /build/tmp.NNtbPQJWy6/build/modinstall
make --silent --keep-going --jobs=48 O=/build/tmp.NNtbPQJWy6/build INSTALL_MOD_STRIP=1 INSTALL_MOD_PATH=/build/tmp.NNtbPQJWy6/build/modinstall ARCH=riscv CROSS_COMPILE=riscv64-linux- LLVM=1 'CC=ccache clang' 'HOSTCC=ccache clang' modules_install
make[3]: *** No rule to make target 'modules.order', needed by '/build/tmp.NNtbPQJWy6/build/modinstall/lib/modules/7.1.0-rc1-00012-gaef6d4988743/modules.order'.
make[3]: *** No rule to make target 'modules.builtin', needed by '/build/tmp.NNtbPQJWy6/build/modinstall/lib/modules/7.1.0-rc1-00012-gaef6d4988743/modules.builtin'.
make[3]: *** No rule to make target 'modules.builtin.modinfo', needed by '/build/tmp.NNtbPQJWy6/build/modinstall/lib/modules/7.1.0-rc1-00012-gaef6d4988743/modules.builtin.modinfo'.
make[3]: Target '__modinst' not remade because of errors.
make[2]: *** [/build/tmpshhsjat6/Makefile:2047: modules_install] Error 2
make[1]: *** [/build/tmpshhsjat6/Makefile:248: __sub-make] Error 2
make[1]: Target 'modules_install' not remade because of errors.
make: *** [Makefile:248: __sub-make] Error 2
make: Target 'modules_install' not remade because of errors.
make --silent --keep-going --jobs=48 O=/build/tmp.NNtbPQJWy6/build INSTALL_DTBS_PATH=/build/tmp.NNtbPQJWy6/build/dtbsinstall/dtbs ARCH=riscv CROSS_COMPILE=riscv64-linux- LLVM=1 'CC=ccache clang' 'HOSTCC=ccache clang' dtbs
rm -rf /build/tmp.NNtbPQJWy6/build/dtbsinstall
mkdir -p /build/tmp.NNtbPQJWy6/build/dtbsinstall/dtbs
make --silent --keep-going --jobs=48 O=/build/tmp.NNtbPQJWy6/build INSTALL_DTBS_PATH=/build/tmp.NNtbPQJWy6/build/dtbsinstall/dtbs ARCH=riscv CROSS_COMPILE=riscv64-linux- LLVM=1 'CC=ccache clang' 'HOSTCC=ccache clang' dtbs_install
tar --sort=name --owner=tuxmake:1000 --group=tuxmake:1000 --mtime=@1779102417 --clamp-mtime -caf /build/tmp.NNtbPQJWy6/build/dtbs.tar -C /build/tmp.NNtbPQJWy6/build/dtbsinstall dtbs
rm -rf /build/tmp.NNtbPQJWy6/build/install_hdr
make --silent --keep-going --jobs=48 O=/build/tmp.NNtbPQJWy6/build INSTALL_HDR_PATH=/build/tmp.NNtbPQJWy6/build/install_hdr/ ARCH=riscv CROSS_COMPILE=riscv64-linux- LLVM=1 'CC=ccache clang' 'HOSTCC=ccache clang' headers_install
tar --sort=name --owner=tuxmake:1000 --group=tuxmake:1000 --mtime=@1779102417 --clamp-mtime -caf /build/tmp.NNtbPQJWy6/build/headers.tar -C /build/tmp.NNtbPQJWy6/build/install_hdr .
warnings/errors:
/build/tmpshhsjat6/arch/riscv/kernel/hw_breakpoint.c:245:16: error: use of undeclared identifier 'RISCV_DBTR_MCSIZEHI_BIT_MASK'; did you mean 'RISCV_DBTR_MCSIZELO_BIT_MASK'?
/build/tmpshhsjat6/arch/riscv/kernel/hw_breakpoint.c:245:16: error: use of undeclared identifier 'RISCV_DBTR_MC_SIZEHI_BIT'; did you mean 'RISCV_DBTR_MC_SIZELO_BIT'?
/build/tmpshhsjat6/arch/riscv/kernel/hw_breakpoint.c:245:16: error: use of undeclared identifier 'RISCV_DBTR_MCSIZEHI_BIT_MASK'; did you mean 'RISCV_DBTR_MCSIZELO_BIT_MASK'?
/build/tmpshhsjat6/arch/riscv/kernel/hw_breakpoint.c:271:17: error: use of undeclared identifier 'RISCV_DBTR_MCSIZEHI_BIT_MASK'; did you mean 'RISCV_DBTR_MCSIZELO_BIT_MASK'?
/build/tmpshhsjat6/arch/riscv/kernel/hw_breakpoint.c:271:17: error: use of undeclared identifier 'RISCV_DBTR_MC_SIZEHI_BIT'; did you mean 'RISCV_DBTR_MC_SIZELO_BIT'?
/build/tmpshhsjat6/arch/riscv/kernel/hw_breakpoint.c:271:17: error: use of undeclared identifier 'RISCV_DBTR_MCSIZEHI_BIT_MASK'; did you mean 'RISCV_DBTR_MCSIZELO_BIT_MASK'?

linux-riscv-bot · 2026-05-18T11:32:52Z

Patch 1: "[v4,1/2] riscv: Introduce support for hardware break/watchpoints"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 1208.38 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:02:59Z

Patch 1: "[v4,1/2] riscv: Introduce support for hardware break/watchpoints"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1805.22 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:03:27Z

Patch 1: "[v4,1/2] riscv: Introduce support for hardware break/watchpoints"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 25.58 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:03:55Z

Patch 1: "[v4,1/2] riscv: Introduce support for hardware break/watchpoints"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 26.89 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:04:01Z

Patch 1: "[v4,1/2] riscv: Introduce support for hardware break/watchpoints"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 3.96 seconds
Result: WARNING
Output:

WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#37: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 1103 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit aef6d4988743 ("riscv: Introduce support for hardware break/watchpoints") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 1 warnings, 0 checks, 1103 lines checked
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?

linux-riscv-bot · 2026-05-18T12:05:30Z

Patch 1: "[v4,1/2] riscv: Introduce support for hardware break/watchpoints"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 86.59 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:05:33Z

Patch 1: "[v4,1/2] riscv: Introduce support for hardware break/watchpoints"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.62 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:05:36Z

Patch 1: "[v4,1/2] riscv: Introduce support for hardware break/watchpoints"
kdoc
Desc: Detects for kdoc errors
Duration: 0.93 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:05:38Z

Patch 1: "[v4,1/2] riscv: Introduce support for hardware break/watchpoints"
module-param
Desc: Detect module_param changes
Duration: 0.27 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:05:41Z

Patch 1: "[v4,1/2] riscv: Introduce support for hardware break/watchpoints"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:05:43Z

Patch 1: "[v4,1/2] riscv: Introduce support for hardware break/watchpoints"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.31 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:08:03Z

Patch 2: "[v4,2/2] riscv: Add breakpoint and watchpoint test for riscv"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 123.66 seconds
Result: ERROR
Output:

Full log:
W: Support for running offline not available (unshare: unshare failed: Operation not permitted)
tuxmake --download-all-korg-gcc-toolchains --target-arch=riscv --kconfig=rv32_defconfig --toolchain=llvm --wrapper=ccache --environment=KBUILD_BUILD_TIMESTAMP=@1621270510 --environment=KBUILD_BUILD_USER=tuxmake --environment=KBUILD_BUILD_HOST=tuxmake --environment=KCFLAGS=-ffile-prefix-map=/build/tmp.arLeYKwFqC/build/= --runtime=null --image=docker.io/tuxmake/riscv_clang CROSS_COMPILE=riscv64-linux- config default kernel xipkernel modules dtbs dtbs-legacy debugkernel headers
make --silent --keep-going --jobs=48 O=/build/tmp.arLeYKwFqC/build ARCH=riscv CROSS_COMPILE=riscv64-linux- LLVM=1 'CC=ccache clang' 'HOSTCC=ccache clang' rv32_defconfig
make --silent --keep-going --jobs=48 O=/build/tmp.arLeYKwFqC/build ARCH=riscv CROSS_COMPILE=riscv64-linux- LLVM=1 'CC=ccache clang' 'HOSTCC=ccache clang'
/build/tmpvd0xhq1p/arch/riscv/kernel/hw_breakpoint.c:245:16: error: use of undeclared identifier 'RISCV_DBTR_MCSIZEHI_BIT_MASK'; did you mean 'RISCV_DBTR_MCSIZELO_BIT_MASK'?
  245 |                 hw->tdata1 = RISCV_DBTR_SET_MC_SIZEHI(hw->tdata1, 0);
      |                              ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:247:14: note: expanded from macro 'RISCV_DBTR_SET_MC_SIZEHI'
  247 |                 mcsht1 &= ~RISCV_DBTR_BIT_MASK(MC, SIZEHI);             \
      |                            ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:32:2: note: expanded from macro 'RISCV_DBTR_BIT_MASK'
   32 |         RISCV_DBTR_##_prefix##_name##_BIT_MASK
      |         ^
<scratch space>:104:1: note: expanded from here
  104 | RISCV_DBTR_MCSIZEHI_BIT_MASK
      | ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:127:2: note: 'RISCV_DBTR_MCSIZELO_BIT_MASK' declared here
  127 |         RISCV_DBTR_BIT_MASK(MC, SIZELO) = RISCV_DBTR_BIT_MASK_VAL(MC, SIZELO, 2),
      |         ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:32:2: note: expanded from macro 'RISCV_DBTR_BIT_MASK'
   32 |         RISCV_DBTR_##_prefix##_name##_BIT_MASK
      |         ^
<scratch space>:61:1: note: expanded from here
   61 | RISCV_DBTR_MCSIZELO_BIT_MASK
      | ^
/build/tmpvd0xhq1p/arch/riscv/kernel/hw_breakpoint.c:245:16: error: use of undeclared identifier 'RISCV_DBTR_MC_SIZEHI_BIT'; did you mean 'RISCV_DBTR_MC_SIZELO_BIT'?
  245 |                 hw->tdata1 = RISCV_DBTR_SET_MC_SIZEHI(hw->tdata1, 0);
      |                              ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:248:25: note: expanded from macro 'RISCV_DBTR_SET_MC_SIZEHI'
  248 |                 mcsht1 |= (((_val) << RISCV_DBTR_BIT(MC, SIZEHI))       \
      |                                       ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:29:2: note: expanded from macro 'RISCV_DBTR_BIT'
   29 |         RISCV_DBTR_##_prefix##_##_name##_BIT
      |         ^
<scratch space>:108:1: note: expanded from here
  108 | RISCV_DBTR_MC_SIZEHI_BIT
      | ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:96:2: note: 'RISCV_DBTR_MC_SIZELO_BIT' declared here
   96 |         RISCV_DBTR_BIT(MC, SIZELO)   = 16,
      |         ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:29:2: note: expanded from macro 'RISCV_DBTR_BIT'
   29 |         RISCV_DBTR_##_prefix##_##_name##_BIT
      |         ^
<scratch space>:166:1: note: expanded from here
  166 | RISCV_DBTR_MC_SIZELO_BIT
      | ^
/build/tmpvd0xhq1p/arch/riscv/kernel/hw_breakpoint.c:245:16: error: use of undeclared identifier 'RISCV_DBTR_MCSIZEHI_BIT_MASK'; did you mean 'RISCV_DBTR_MCSIZELO_BIT_MASK'?
  245 |                 hw->tdata1 = RISCV_DBTR_SET_MC_SIZEHI(hw->tdata1, 0);
      |                              ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:249:9: note: expanded from macro 'RISCV_DBTR_SET_MC_SIZEHI'
  249 |                            & RISCV_DBTR_BIT_MASK(MC, SIZEHI));          \
      |                              ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:32:2: note: expanded from macro 'RISCV_DBTR_BIT_MASK'
   32 |         RISCV_DBTR_##_prefix##_name##_BIT_MASK
      |         ^
<scratch space>:111:1: note: expanded from here
  111 | RISCV_DBTR_MCSIZEHI_BIT_MASK
      | ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:127:2: note: 'RISCV_DBTR_MCSIZELO_BIT_MASK' declared here
  127 |         RISCV_DBTR_BIT_MASK(MC, SIZELO) = RISCV_DBTR_BIT_MASK_VAL(MC, SIZELO, 2),
      |         ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:32:2: note: expanded from macro 'RISCV_DBTR_BIT_MASK'
   32 |         RISCV_DBTR_##_prefix##_name##_BIT_MASK
      |         ^
<scratch space>:61:1: note: expanded from here
   61 | RISCV_DBTR_MCSIZELO_BIT_MASK
      | ^
/build/tmpvd0xhq1p/arch/riscv/kernel/hw_breakpoint.c:271:17: error: use of undeclared identifier 'RISCV_DBTR_MCSIZEHI_BIT_MASK'; did you mean 'RISCV_DBTR_MCSIZELO_BIT_MASK'?
  271 |                         hw->tdata1 = RISCV_DBTR_SET_MC_SIZEHI(hw->tdata1, 0);
      |                                      ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:247:14: note: expanded from macro 'RISCV_DBTR_SET_MC_SIZEHI'
  247 |                 mcsht1 &= ~RISCV_DBTR_BIT_MASK(MC, SIZEHI);             \
      |                            ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:32:2: note: expanded from macro 'RISCV_DBTR_BIT_MASK'
   32 |         RISCV_DBTR_##_prefix##_name##_BIT_MASK
      |         ^
<scratch space>:154:1: note: expanded from here
  154 | RISCV_DBTR_MCSIZEHI_BIT_MASK
      | ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:127:2: note: 'RISCV_DBTR_MCSIZELO_BIT_MASK' declared here
  127 |         RISCV_DBTR_BIT_MASK(MC, SIZELO) = RISCV_DBTR_BIT_MASK_VAL(MC, SIZELO, 2),
      |         ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:32:2: note: expanded from macro 'RISCV_DBTR_BIT_MASK'
   32 |         RISCV_DBTR_##_prefix##_name##_BIT_MASK
      |         ^
<scratch space>:61:1: note: expanded from here
   61 | RISCV_DBTR_MCSIZELO_BIT_MASK
      | ^
/build/tmpvd0xhq1p/arch/riscv/kernel/hw_breakpoint.c:271:17: error: use of undeclared identifier 'RISCV_DBTR_MC_SIZEHI_BIT'; did you mean 'RISCV_DBTR_MC_SIZELO_BIT'?
  271 |                         hw->tdata1 = RISCV_DBTR_SET_MC_SIZEHI(hw->tdata1, 0);
      |                                      ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:248:25: note: expanded from macro 'RISCV_DBTR_SET_MC_SIZEHI'
  248 |                 mcsht1 |= (((_val) << RISCV_DBTR_BIT(MC, SIZEHI))       \
      |                                       ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:29:2: note: expanded from macro 'RISCV_DBTR_BIT'
   29 |         RISCV_DBTR_##_prefix##_##_name##_BIT
      |         ^
<scratch space>:158:1: note: expanded from here
  158 | RISCV_DBTR_MC_SIZEHI_BIT
      | ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:96:2: note: 'RISCV_DBTR_MC_SIZELO_BIT' declared here
   96 |         RISCV_DBTR_BIT(MC, SIZELO)   = 16,
      |         ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:29:2: note: expanded from macro 'RISCV_DBTR_BIT'
   29 |         RISCV_DBTR_##_prefix##_##_name##_BIT
      |         ^
<scratch space>:166:1: note: expanded from here
  166 | RISCV_DBTR_MC_SIZELO_BIT
      | ^
/build/tmpvd0xhq1p/arch/riscv/kernel/hw_breakpoint.c:271:17: error: use of undeclared identifier 'RISCV_DBTR_MCSIZEHI_BIT_MASK'; did you mean 'RISCV_DBTR_MCSIZELO_BIT_MASK'?
  271 |                         hw->tdata1 = RISCV_DBTR_SET_MC_SIZEHI(hw->tdata1, 0);
      |                                      ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:249:9: note: expanded from macro 'RISCV_DBTR_SET_MC_SIZEHI'
  249 |                            & RISCV_DBTR_BIT_MASK(MC, SIZEHI));          \
      |                              ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:32:2: note: expanded from macro 'RISCV_DBTR_BIT_MASK'
   32 |         RISCV_DBTR_##_prefix##_name##_BIT_MASK
      |         ^
<scratch space>:161:1: note: expanded from here
  161 | RISCV_DBTR_MCSIZEHI_BIT_MASK
      | ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:127:2: note: 'RISCV_DBTR_MCSIZELO_BIT_MASK' declared here
I: config: PASS in 0:00:33.252019
I: default: FAIL in 0:01:23.393850
I: kernel: SKIP in 0:00:00.000007
I: xipkernel: SKIP in 0:00:00.000005
I: modules: FAIL in 0:00:00.092491
I: dtbs: PASS in 0:00:01.805379
I: dtbs-legacy: SKIP in 0:00:00.004844
I: debugkernel: SKIP in 0:00:00.000004
I: headers: PASS in 0:00:01.033639
I: build output in /build/tmp.arLeYKwFqC
  127 |         RISCV_DBTR_BIT_MASK(MC, SIZELO) = RISCV_DBTR_BIT_MASK_VAL(MC, SIZELO, 2),
      |         ^
/build/tmpvd0xhq1p/arch/riscv/include/asm/hw_breakpoint.h:32:2: note: expanded from macro 'RISCV_DBTR_BIT_MASK'
   32 |         RISCV_DBTR_##_prefix##_name##_BIT_MASK
      |         ^
<scratch space>:61:1: note: expanded from here
   61 | RISCV_DBTR_MCSIZELO_BIT_MASK
      | ^
6 errors generated.
make[5]: *** [/build/tmpvd0xhq1p/scripts/Makefile.build:289: arch/riscv/kernel/hw_breakpoint.o] Error 1
make[5]: Target 'arch/riscv/kernel/' not remade because of errors.
make[4]: *** [/build/tmpvd0xhq1p/scripts/Makefile.build:548: arch/riscv/kernel] Error 2
make[4]: Target 'arch/riscv/' not remade because of errors.
make[3]: *** [/build/tmpvd0xhq1p/scripts/Makefile.build:548: arch/riscv] Error 2
make[3]: Target './' not remade because of errors.
make[2]: *** [/build/tmpvd0xhq1p/Makefile:2141: .] Error 2
make[2]: Target '__all' not remade because of errors.
make[1]: *** [/build/tmpvd0xhq1p/Makefile:248: __sub-make] Error 2
make[1]: Target '__all' not remade because of errors.
make: *** [Makefile:248: __sub-make] Error 2
make: Target '__all' not remade because of errors.
rm -rf /build/tmp.arLeYKwFqC/build/modinstall
make --silent --keep-going --jobs=48 O=/build/tmp.arLeYKwFqC/build INSTALL_MOD_STRIP=1 INSTALL_MOD_PATH=/build/tmp.arLeYKwFqC/build/modinstall ARCH=riscv CROSS_COMPILE=riscv64-linux- LLVM=1 'CC=ccache clang' 'HOSTCC=ccache clang' modules_install
make[3]: *** No rule to make target 'modules.order', needed by '/build/tmp.arLeYKwFqC/build/modinstall/lib/modules/7.1.0-rc1-00013-ga3a9cd04861c/modules.order'.
make[3]: *** No rule to make target 'modules.builtin', needed by '/build/tmp.arLeYKwFqC/build/modinstall/lib/modules/7.1.0-rc1-00013-ga3a9cd04861c/modules.builtin'.
make[3]: *** No rule to make target 'modules.builtin.modinfo', needed by '/build/tmp.arLeYKwFqC/build/modinstall/lib/modules/7.1.0-rc1-00013-ga3a9cd04861c/modules.builtin.modinfo'.
make[3]: Target '__modinst' not remade because of errors.
make[2]: *** [/build/tmpvd0xhq1p/Makefile:2047: modules_install] Error 2
make[1]: *** [/build/tmpvd0xhq1p/Makefile:248: __sub-make] Error 2
make[1]: Target 'modules_install' not remade because of errors.
make: *** [Makefile:248: __sub-make] Error 2
make: Target 'modules_install' not remade because of errors.
make --silent --keep-going --jobs=48 O=/build/tmp.arLeYKwFqC/build INSTALL_DTBS_PATH=/build/tmp.arLeYKwFqC/build/dtbsinstall/dtbs ARCH=riscv CROSS_COMPILE=riscv64-linux- LLVM=1 'CC=ccache clang' 'HOSTCC=ccache clang' dtbs
rm -rf /build/tmp.arLeYKwFqC/build/dtbsinstall
mkdir -p /build/tmp.arLeYKwFqC/build/dtbsinstall/dtbs
make --silent --keep-going --jobs=48 O=/build/tmp.arLeYKwFqC/build INSTALL_DTBS_PATH=/build/tmp.arLeYKwFqC/build/dtbsinstall/dtbs ARCH=riscv CROSS_COMPILE=riscv64-linux- LLVM=1 'CC=ccache clang' 'HOSTCC=ccache clang' dtbs_install
tar --sort=name --owner=tuxmake:1000 --group=tuxmake:1000 --mtime=@1779102417 --clamp-mtime -caf /build/tmp.arLeYKwFqC/build/dtbs.tar -C /build/tmp.arLeYKwFqC/build/dtbsinstall dtbs
rm -rf /build/tmp.arLeYKwFqC/build/install_hdr
make --silent --keep-going --jobs=48 O=/build/tmp.arLeYKwFqC/build INSTALL_HDR_PATH=/build/tmp.arLeYKwFqC/build/install_hdr/ ARCH=riscv CROSS_COMPILE=riscv64-linux- LLVM=1 'CC=ccache clang' 'HOSTCC=ccache clang' headers_install
tar --sort=name --owner=tuxmake:1000 --group=tuxmake:1000 --mtime=@1779102417 --clamp-mtime -caf /build/tmp.arLeYKwFqC/build/headers.tar -C /build/tmp.arLeYKwFqC/build/install_hdr .
warnings/errors:
/build/tmpvd0xhq1p/arch/riscv/kernel/hw_breakpoint.c:245:16: error: use of undeclared identifier 'RISCV_DBTR_MCSIZEHI_BIT_MASK'; did you mean 'RISCV_DBTR_MCSIZELO_BIT_MASK'?
/build/tmpvd0xhq1p/arch/riscv/kernel/hw_breakpoint.c:245:16: error: use of undeclared identifier 'RISCV_DBTR_MC_SIZEHI_BIT'; did you mean 'RISCV_DBTR_MC_SIZELO_BIT'?
/build/tmpvd0xhq1p/arch/riscv/kernel/hw_breakpoint.c:245:16: error: use of undeclared identifier 'RISCV_DBTR_MCSIZEHI_BIT_MASK'; did you mean 'RISCV_DBTR_MCSIZELO_BIT_MASK'?
/build/tmpvd0xhq1p/arch/riscv/kernel/hw_breakpoint.c:271:17: error: use of undeclared identifier 'RISCV_DBTR_MCSIZEHI_BIT_MASK'; did you mean 'RISCV_DBTR_MCSIZELO_BIT_MASK'?
/build/tmpvd0xhq1p/arch/riscv/kernel/hw_breakpoint.c:271:17: error: use of undeclared identifier 'RISCV_DBTR_MC_SIZEHI_BIT'; did you mean 'RISCV_DBTR_MC_SIZELO_BIT'?
/build/tmpvd0xhq1p/arch/riscv/kernel/hw_breakpoint.c:271:17: error: use of undeclared identifier 'RISCV_DBTR_MCSIZEHI_BIT_MASK'; did you mean 'RISCV_DBTR_MCSIZELO_BIT_MASK'?

linux-riscv-bot · 2026-05-18T12:25:04Z

Patch 2: "[v4,2/2] riscv: Add breakpoint and watchpoint test for riscv"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 1018.58 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:48:10Z

Patch 2: "[v4,2/2] riscv: Add breakpoint and watchpoint test for riscv"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1383.89 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:48:37Z

Patch 2: "[v4,2/2] riscv: Add breakpoint and watchpoint test for riscv"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 25.76 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:49:05Z

Patch 2: "[v4,2/2] riscv: Add breakpoint and watchpoint test for riscv"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 26.49 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:49:10Z

Patch 2: "[v4,2/2] riscv: Add breakpoint and watchpoint test for riscv"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 2.34 seconds
Result: WARNING
Output:

WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#33: 
new file mode 100644

WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst
#65: FILE: tools/testing/selftests/breakpoints/breakpoint_test_riscv.c:28:
+static volatile int test_func_sink;

WARNING: Prefer noinline over __attribute__((noinline))
#140: FILE: tools/testing/selftests/breakpoints/breakpoint_test_riscv.c:103:
+static __attribute__((noinline)) void test_func(void)

total: 0 errors, 3 warnings, 0 checks, 224 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit a3a9cd04861c ("riscv: Add breakpoint and watchpoint test for riscv") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 3 warnings, 0 checks, 224 lines checked
WARNING: Prefer noinline over __attribute__((noinline))
WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?

linux-riscv-bot · 2026-05-18T12:50:38Z

Patch 2: "[v4,2/2] riscv: Add breakpoint and watchpoint test for riscv"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 85.88 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:50:40Z

Patch 2: "[v4,2/2] riscv: Add breakpoint and watchpoint test for riscv"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.25 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:50:43Z

Patch 2: "[v4,2/2] riscv: Add breakpoint and watchpoint test for riscv"
kdoc
Desc: Detects for kdoc errors
Duration: 0.93 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:50:45Z

Patch 2: "[v4,2/2] riscv: Add breakpoint and watchpoint test for riscv"
module-param
Desc: Detect module_param changes
Duration: 0.27 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:50:47Z

Patch 2: "[v4,2/2] riscv: Add breakpoint and watchpoint test for riscv"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.24 seconds
Result: PASS

linux-riscv-bot · 2026-05-18T12:50:49Z

Patch 2: "[v4,2/2] riscv: Add breakpoint and watchpoint test for riscv"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.31 seconds
Result: PASS

Linux RISC-V bot and others added 3 commits May 14, 2026 08:49

Adding CI files

cd9d421

linux-riscv-bot force-pushed the workflow__riscv__fixes branch 2 times, most recently from a1231b7 to c03cdce Compare May 23, 2026 03:29

linux-riscv-bot closed this May 26, 2026

linux-riscv-bot deleted the pw1096361 branch May 26, 2026 00:04

Conversation

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

linux-riscv-bot commented May 18, 2026

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

2 participants