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[PW_SID:1098046] [v3] perf riscv: Add SDT argument parsing for RISC-V#1983

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[PW_SID:1098046] [v3] perf riscv: Add SDT argument parsing for RISC-V#1983
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PR for series 1098046 applied to workflow__riscv__fixes

Name: [v3] perf riscv: Add SDT argument parsing for RISC-V
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1098046
Version: 3

Linux RISC-V bot and others added 2 commits May 14, 2026 08:49
Implement __perf_sdt_arg_parse_op_riscv() to convert RISC-V GCC-generated
SDT probe operands into uprobe-compatible format, and register it in the
perf_sdt_arg_parse_op() dispatcher for EM_RISCV.

RISC-V GCC uses the 'nor' constraint for SDT arguments, producing operands
in the following formats:

  Format       Example      Uprobe format
  -----------  -----------  -------------
  register     a0           %a0
  memory (+)   8(a0)        +8(%a0)
  memory (-)   -20(s0)      -20(%s0)
  constant     99           (skip, not supported by uprobe)

Key differences from other architectures:
 - Register names use ABI aliases (a0-a7, t0-t6, s0-s11, sp, ra, etc.)
   without any '%' prefix, unlike x86 (%rax) or arm64 (x0).
 - Memory operands use OFFSET(REG) syntax where OFFSET may be negative,
   unlike arm64's [sp, NUM] or powerpc's NUM(%rREG).

Two regexes are used:
 - SDT_OP_REGEX1: matches RISC-V ABI register names saved in pt_regs
 - SDT_OP_REGEX2: matches [-]NUM(REG) memory operands

Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v3] perf riscv: Add SDT argument parsing for RISC-V"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 114.68 seconds
Result: PASS

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Patch 1: "[v3] perf riscv: Add SDT argument parsing for RISC-V"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 1015.21 seconds
Result: PASS

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Patch 1: "[v3] perf riscv: Add SDT argument parsing for RISC-V"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1371.78 seconds
Result: PASS

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Patch 1: "[v3] perf riscv: Add SDT argument parsing for RISC-V"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 19.31 seconds
Result: PASS

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Patch 1: "[v3] perf riscv: Add SDT argument parsing for RISC-V"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 20.80 seconds
Result: PASS

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Patch 1: "[v3] perf riscv: Add SDT argument parsing for RISC-V"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 2.10 seconds
Result: WARNING
Output:

CHECK: Comparison to NULL could be written "!strchr"
#128: FILE: tools/perf/util/perf-regs-arch/perf_regs_riscv.c:84:
+	if (strchr(old_op, '(') == NULL &&

CHECK: Alignment should match open parenthesis
#149: FILE: tools/perf/util/perf-regs-arch/perf_regs_riscv.c:105:
+		scnprintf(*new_op, new_len, "%%%.*s",
+			(int)(rm[1].rm_eo - rm[1].rm_so), old_op + rm[1].rm_so);

CHECK: Alignment should match open parenthesis
#168: FILE: tools/perf/util/perf-regs-arch/perf_regs_riscv.c:124:
+		scnprintf(*new_op, new_len, "%c%.*s(%%%.*s)", prefix,
+			(int)(rm[2].rm_eo - rm[2].rm_so), old_op + rm[2].rm_so,

total: 0 errors, 0 warnings, 3 checks, 152 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit 556795f4125d ("perf riscv: Add SDT argument parsing for RISC-V") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 0 warnings, 3 checks, 152 lines checked
CHECK: Alignment should match open parenthesis
CHECK: Comparison to NULL could be written "!strchr"


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Patch 1: "[v3] perf riscv: Add SDT argument parsing for RISC-V"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 77.55 seconds
Result: PASS

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Patch 1: "[v3] perf riscv: Add SDT argument parsing for RISC-V"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.23 seconds
Result: PASS

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Patch 1: "[v3] perf riscv: Add SDT argument parsing for RISC-V"
kdoc
Desc: Detects for kdoc errors
Duration: 0.71 seconds
Result: PASS

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Patch 1: "[v3] perf riscv: Add SDT argument parsing for RISC-V"
module-param
Desc: Detect module_param changes
Duration: 0.24 seconds
Result: PASS

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Patch 1: "[v3] perf riscv: Add SDT argument parsing for RISC-V"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.23 seconds
Result: PASS

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Patch 1: "[v3] perf riscv: Add SDT argument parsing for RISC-V"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.26 seconds
Result: PASS

@linux-riscv-bot linux-riscv-bot force-pushed the workflow__riscv__fixes branch from cd9d421 to a1231b7 Compare May 22, 2026 06:39
@linux-riscv-bot linux-riscv-bot deleted the pw1098046 branch May 23, 2026 00:07
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