[PW_SID:1098934] riscv: optimize Vector context restore on syscall#1992
[PW_SID:1098934] riscv: optimize Vector context restore on syscall#1992linux-riscv-bot wants to merge 4 commits into
Conversation
Lift riscv_v_{enable,disable} out of __*vstate_{save,restore,discard} so
that we can reuse some functions without repeatedly turning on/off
vector.
Also, refactor and document about the user context save in preempt_v to
make code more readable.
Signed-off-by: Andy Chiu <tchiu@tenstorrent.com>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The RISC-V vector specification states that executing a system call causes all caller-saved vector registers (v0-v31, vl, vtype) and vstart to become unspecified. Currently, after calling riscv_v_vstate_discard(), the vector state may still be marked as DIRTY, which can mislead the context switch logic into treating the registers as containing valid user data. This patch clarifies and tightens the kernel-side semantics: 1. On syscall entry, the kernel checks the vector state via sstatus and explicitly set it to INIT, indicating that the vector registers no longer contain meaningful user data. 2. During context switch, the vector state is saved only if the state is DIRTY. (no change) 3. On restore, if the state is INIT, the vector registers are treated as invalid and are not restored from memory. Instead, they are overwritten with a known initial value to avoid data leaakge. Signed-off-by: daichengrong <daichengrong@iscas.ac.cn> Co-developed-by: Andy Chiu <tchiu@tenstorrent.com> Signed-off-by: Andy Chiu <tchiu@tenstorrent.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The last patch introduced the INITIAL vector state to avoid saving and restoring vector registers across syscall boundaries. However, this optimization did not fully account for the ptrace and signal handling interfaces. As a result, two issues emerged: 1. Ptrace reads at syscall stop could observe stale, non-nulled registers. 2. Modifications to the ucontext through signal interface during a syscall stop would be overwritten by the vector discaring macro. This patch introduces riscv_v_ucontext_save() to synchronize these paths with the INITIAL state: - Ptrace reads during a syscall stop now explicitly execute the hardware discard macro and return the discarded state to prevent data leaks. - Ptrace writes (PTRACE_SETREGSET) during a syscall stop are silently dropped (returning 0). Returning an error like EINVAL would break debbugers like GDB, which disables the optional regset on receiving such error. - Signal handling (rt_sigreturn) now honor user-space modifications to the vector context (for user-space thread schedulers). CC: Sergey Matyukevich <geomatsi@gmail.com> CC: gdb@sourceware.org Signed-off-by: Andy Chiu <tchiu@tenstorrent.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add new test cases to verify the vector state restorations at syscall stops for ptrace and signal interfaces. Specifically: 1. Signal handler should read all ones at syscall stop and modifying context should success. 2. Ptrace should read all ones but any modification to NT_RISCV_VECTOR is silently dropped. Signed-off-by: Andy Chiu <tchiu@tenstorrent.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
|
Patch 1: "[v3,1/4] riscv: vector: refactor vector context operations" |
|
Patch 1: "[v3,1/4] riscv: vector: refactor vector context operations" |
|
Patch 1: "[v3,1/4] riscv: vector: refactor vector context operations" |
|
Patch 1: "[v3,1/4] riscv: vector: refactor vector context operations" |
|
Patch 1: "[v3,1/4] riscv: vector: refactor vector context operations" |
|
Patch 1: "[v3,1/4] riscv: vector: refactor vector context operations" |
|
Patch 1: "[v3,1/4] riscv: vector: refactor vector context operations" |
|
Patch 1: "[v3,1/4] riscv: vector: refactor vector context operations" |
|
Patch 1: "[v3,1/4] riscv: vector: refactor vector context operations" |
|
Patch 1: "[v3,1/4] riscv: vector: refactor vector context operations" |
|
Patch 1: "[v3,1/4] riscv: vector: refactor vector context operations" |
|
Patch 1: "[v3,1/4] riscv: vector: refactor vector context operations" |
|
Patch 2: "[v3,2/4] riscv: clarify vector state semantics on syscall and context switch" |
|
Patch 2: "[v3,2/4] riscv: clarify vector state semantics on syscall and context switch" |
|
Patch 2: "[v3,2/4] riscv: clarify vector state semantics on syscall and context switch" |
|
Patch 2: "[v3,2/4] riscv: clarify vector state semantics on syscall and context switch" |
|
Patch 2: "[v3,2/4] riscv: clarify vector state semantics on syscall and context switch" |
|
Patch 2: "[v3,2/4] riscv: clarify vector state semantics on syscall and context switch" |
|
Patch 2: "[v3,2/4] riscv: clarify vector state semantics on syscall and context switch" |
|
Patch 2: "[v3,2/4] riscv: clarify vector state semantics on syscall and context switch" |
|
Patch 2: "[v3,2/4] riscv: clarify vector state semantics on syscall and context switch" |
|
Patch 2: "[v3,2/4] riscv: clarify vector state semantics on syscall and context switch" |
|
Patch 2: "[v3,2/4] riscv: clarify vector state semantics on syscall and context switch" |
|
Patch 2: "[v3,2/4] riscv: clarify vector state semantics on syscall and context switch" |
|
Patch 3: "[v3,3/4] riscv: vector: adjust ptrace and signal behavior for INITIAL state" |
|
Patch 3: "[v3,3/4] riscv: vector: adjust ptrace and signal behavior for INITIAL state" |
|
Patch 3: "[v3,3/4] riscv: vector: adjust ptrace and signal behavior for INITIAL state" |
|
Patch 3: "[v3,3/4] riscv: vector: adjust ptrace and signal behavior for INITIAL state" |
|
Patch 3: "[v3,3/4] riscv: vector: adjust ptrace and signal behavior for INITIAL state" |
|
Patch 3: "[v3,3/4] riscv: vector: adjust ptrace and signal behavior for INITIAL state" |
|
Patch 3: "[v3,3/4] riscv: vector: adjust ptrace and signal behavior for INITIAL state" |
|
Patch 3: "[v3,3/4] riscv: vector: adjust ptrace and signal behavior for INITIAL state" |
|
Patch 3: "[v3,3/4] riscv: vector: adjust ptrace and signal behavior for INITIAL state" |
|
Patch 3: "[v3,3/4] riscv: vector: adjust ptrace and signal behavior for INITIAL state" |
|
Patch 3: "[v3,3/4] riscv: vector: adjust ptrace and signal behavior for INITIAL state" |
|
Patch 3: "[v3,3/4] riscv: vector: adjust ptrace and signal behavior for INITIAL state" |
|
Patch 4: "[v3,4/4] selftests: riscv: extend vector tests for sigreturn and ptrace" |
|
Patch 4: "[v3,4/4] selftests: riscv: extend vector tests for sigreturn and ptrace" |
|
Patch 4: "[v3,4/4] selftests: riscv: extend vector tests for sigreturn and ptrace" |
|
Patch 4: "[v3,4/4] selftests: riscv: extend vector tests for sigreturn and ptrace" |
|
Patch 4: "[v3,4/4] selftests: riscv: extend vector tests for sigreturn and ptrace" |
|
Patch 4: "[v3,4/4] selftests: riscv: extend vector tests for sigreturn and ptrace" |
|
Patch 4: "[v3,4/4] selftests: riscv: extend vector tests for sigreturn and ptrace" |
|
Patch 4: "[v3,4/4] selftests: riscv: extend vector tests for sigreturn and ptrace" |
|
Patch 4: "[v3,4/4] selftests: riscv: extend vector tests for sigreturn and ptrace" |
|
Patch 4: "[v3,4/4] selftests: riscv: extend vector tests for sigreturn and ptrace" |
|
Patch 4: "[v3,4/4] selftests: riscv: extend vector tests for sigreturn and ptrace" |
|
Patch 4: "[v3,4/4] selftests: riscv: extend vector tests for sigreturn and ptrace" |
2 participants
PR for series 1098934 applied to workflow__riscv__fixes
Name: riscv: optimize Vector context restore on syscall
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1098934
Version: 3