[PW_SID:955846] riscv: misaligned: fix interruptible context and add tests by linux-riscv-bot · Pull Request #329 · linux-riscv/linux

linux-riscv-bot · 2025-04-22T20:20:59Z

PR for series 955846 applied to workflow__riscv__fixes

Name: riscv: misaligned: fix interruptible context and add tests
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=955846
Version: 2

Since both load/store and user/kernel should use almost the same path and that we are going to add some code around that, factorize it. Signed-off-by: Clément Léger <cleger@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

We can safely reenable IRQs if coming from userspace. This allows to access user memory that could potentially trigger a page fault. Fixes: b686ecd ("riscv: misaligned: Restrict user access to kernel memory") Signed-off-by: Clément Léger <cleger@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Now that we can safely handle user memory accesses while in the misaligned access handlers, use get_user() instead of __get_user() to have user memory access checks. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

riscv supports the "unaligned-trap" sysctl variable, add it to the list of supported architectures. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

This selftest tests (almost) all the currently emulated instruction (except for the RV32 compressed ones which are left as a future exercise for a RV32 user). For the FPU instructions, all the FPU registers are tested. Signed-off-by: Clément Léger <cleger@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

linux-riscv-bot · 2025-04-22T20:24:15Z

Patch 1: "[v2,1/5] riscv: misaligned: factorize trap handling"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 102.60 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T20:40:01Z

Patch 1: "[v2,1/5] riscv: misaligned: factorize trap handling"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 944.56 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:00:55Z

Patch 1: "[v2,1/5] riscv: misaligned: factorize trap handling"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1252.25 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:01:17Z

Patch 1: "[v2,1/5] riscv: misaligned: factorize trap handling"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 20.33 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:01:40Z

Patch 1: "[v2,1/5] riscv: misaligned: factorize trap handling"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 21.02 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:01:42Z

Patch 1: "[v2,1/5] riscv: misaligned: factorize trap handling"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 1.42 seconds
Result: WARNING
Output:

CHECK: Please use a blank line after function/struct/union/enum declarations
#31: FILE: arch/riscv/kernel/traps.c:205:
+};
+static const struct {

total: 0 errors, 0 warnings, 1 checks, 83 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit d980e0a12d3a ("riscv: misaligned: factorize trap handling") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 0 warnings, 1 checks, 83 lines checked
CHECK: Please use a blank line after function/struct/union/enum declarations

linux-riscv-bot · 2025-04-22T21:02:23Z

Patch 1: "[v2,1/5] riscv: misaligned: factorize trap handling"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 39.21 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:02:25Z

Patch 1: "[v2,1/5] riscv: misaligned: factorize trap handling"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.28 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:02:28Z

Patch 1: "[v2,1/5] riscv: misaligned: factorize trap handling"
kdoc
Desc: Detects for kdoc errors
Duration: 0.90 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:02:29Z

Patch 1: "[v2,1/5] riscv: misaligned: factorize trap handling"
module-param
Desc: Detect module_param changes
Duration: 0.24 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:02:31Z

Patch 1: "[v2,1/5] riscv: misaligned: factorize trap handling"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.22 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:02:33Z

Patch 1: "[v2,1/5] riscv: misaligned: factorize trap handling"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.29 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:04:30Z

Patch 2: "[v2,2/5] riscv: misaligned: enable IRQs while handling misaligned accesses"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 101.73 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:20:12Z

Patch 2: "[v2,2/5] riscv: misaligned: enable IRQs while handling misaligned accesses"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 940.92 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:41:05Z

Patch 2: "[v2,2/5] riscv: misaligned: enable IRQs while handling misaligned accesses"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1251.49 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:41:27Z

Patch 2: "[v2,2/5] riscv: misaligned: enable IRQs while handling misaligned accesses"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 20.36 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:41:50Z

Patch 2: "[v2,2/5] riscv: misaligned: enable IRQs while handling misaligned accesses"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 21.05 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:41:52Z

Patch 2: "[v2,2/5] riscv: misaligned: enable IRQs while handling misaligned accesses"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 0.75 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:42:32Z

Patch 2: "[v2,2/5] riscv: misaligned: enable IRQs while handling misaligned accesses"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 38.47 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:42:34Z

Patch 2: "[v2,2/5] riscv: misaligned: enable IRQs while handling misaligned accesses"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.22 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:42:36Z

Patch 2: "[v2,2/5] riscv: misaligned: enable IRQs while handling misaligned accesses"
kdoc
Desc: Detects for kdoc errors
Duration: 0.91 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:42:38Z

Patch 2: "[v2,2/5] riscv: misaligned: enable IRQs while handling misaligned accesses"
module-param
Desc: Detect module_param changes
Duration: 0.24 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:42:40Z

Patch 2: "[v2,2/5] riscv: misaligned: enable IRQs while handling misaligned accesses"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.26 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T21:42:42Z

Patch 2: "[v2,2/5] riscv: misaligned: enable IRQs while handling misaligned accesses"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.29 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T22:22:49Z

Patch 3: "[v2,3/5] riscv: misaligned: use get_user() instead of __get_user()"
module-param
Desc: Detect module_param changes
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T22:22:51Z

Patch 3: "[v2,3/5] riscv: misaligned: use get_user() instead of __get_user()"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.21 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T22:22:52Z

Patch 3: "[v2,3/5] riscv: misaligned: use get_user() instead of __get_user()"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.29 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T22:24:50Z

Patch 4: "[v2,4/5] Documentation/sysctl: add riscv to unaligned-trap supported archs"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 102.66 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T22:39:19Z

Patch 4: "[v2,4/5] Documentation/sysctl: add riscv to unaligned-trap supported archs"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 866.86 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T22:58:29Z

Patch 4: "[v2,4/5] Documentation/sysctl: add riscv to unaligned-trap supported archs"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1148.37 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T22:58:50Z

Patch 4: "[v2,4/5] Documentation/sysctl: add riscv to unaligned-trap supported archs"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 19.91 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T22:59:13Z

Patch 4: "[v2,4/5] Documentation/sysctl: add riscv to unaligned-trap supported archs"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 21.53 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T22:59:15Z

Patch 4: "[v2,4/5] Documentation/sysctl: add riscv to unaligned-trap supported archs"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 0.67 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T22:59:56Z

Patch 4: "[v2,4/5] Documentation/sysctl: add riscv to unaligned-trap supported archs"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 38.82 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T22:59:57Z

Patch 4: "[v2,4/5] Documentation/sysctl: add riscv to unaligned-trap supported archs"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T23:00:00Z

Patch 4: "[v2,4/5] Documentation/sysctl: add riscv to unaligned-trap supported archs"
kdoc
Desc: Detects for kdoc errors
Duration: 1.16 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T23:00:02Z

Patch 4: "[v2,4/5] Documentation/sysctl: add riscv to unaligned-trap supported archs"
module-param
Desc: Detect module_param changes
Duration: 0.25 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T23:00:04Z

Patch 4: "[v2,4/5] Documentation/sysctl: add riscv to unaligned-trap supported archs"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T23:00:06Z

Patch 4: "[v2,4/5] Documentation/sysctl: add riscv to unaligned-trap supported archs"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.29 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T23:02:03Z

Patch 5: "[v2,5/5] selftests: riscv: add misaligned access testing"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 101.95 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T23:16:33Z

Patch 5: "[v2,5/5] selftests: riscv: add misaligned access testing"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 867.62 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T23:35:42Z

Patch 5: "[v2,5/5] selftests: riscv: add misaligned access testing"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1147.73 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T23:36:03Z

Patch 5: "[v2,5/5] selftests: riscv: add misaligned access testing"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 20.18 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T23:36:26Z

Patch 5: "[v2,5/5] selftests: riscv: add misaligned access testing"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 20.83 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T23:36:30Z

Patch 5: "[v2,5/5] selftests: riscv: add misaligned access testing"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 3.56 seconds
Result: ERROR
Output:

WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#32: 
new file mode 100644

WARNING: 'ment' may be misspelled - perhaps 'meant'?
#67: FILE: tools/testing/selftests/riscv/misaligned/common.S:6:
+ *     Clément Léger <cleger@rivosinc.com>
            ^^^^

WARNING: 'ment' may be misspelled - perhaps 'meant'?
#106: FILE: tools/testing/selftests/riscv/misaligned/fpu.S:6:
+ *     Clément Léger <cleger@rivosinc.com>
            ^^^^

WARNING: 'ment' may be misspelled - perhaps 'meant'?
#292: FILE: tools/testing/selftests/riscv/misaligned/gp.S:6:
+ *     Clément Léger <cleger@rivosinc.com>
            ^^^^

WARNING: 'ment' may be misspelled - perhaps 'meant'?
#401: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:6:
+ *     Clément Léger <cleger@rivosinc.com>
            ^^^^

ERROR: Macros with complex values should be enclosed in parentheses
#466: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:71:
+#define fpu_load_proto(__inst, __type) \
+extern __type test_ ## __inst(unsigned long fp_reg, void *addr, unsigned long offset, __type value)

ERROR: Macros with complex values should be enclosed in parentheses
#484: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:89:
+#define gp_load_proto(__inst, __type) \
+extern __type test_ ## __inst(void *addr, unsigned long offset, __type value)

ERROR: Macros with complex values should be enclosed in parentheses
#506: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:111:
+#define TEST_GP_LOAD(__inst, __type_size)					\
+TEST(gp_load_ ## __inst)							\
+{										\
+	int offset, ret;							\
+	uint8_t buf[16] __attribute__((aligned(16)));				\
+										\
+	ret = prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT);			\
+	ASSERT_EQ(ret, 0);							\
+										\
+	for (offset = 1; offset < __type_size / 8; offset++) {			\
+		uint ## __type_size ## _t val = VAL ## __type_size;		\
+		uint ## __type_size ## _t *ptr = (uint ## __type_size ## _t *) (buf + offset); \
+		memcpy(ptr, &val, sizeof(val));					\
+		val = test_ ## __inst(ptr, offset, val);			\
+		EXPECT_EQ(VAL ## __type_size, val);				\
+	}									\
+}

CHECK: Macro argument '__type_size' may be better as '(__type_size)' to avoid precedence issues
#506: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:111:
+#define TEST_GP_LOAD(__inst, __type_size)					\
+TEST(gp_load_ ## __inst)							\
+{										\
+	int offset, ret;							\
+	uint8_t buf[16] __attribute__((aligned(16)));				\
+										\
+	ret = prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT);			\
+	ASSERT_EQ(ret, 0);							\
+										\
+	for (offset = 1; offset < __type_size / 8; offset++) {			\
+		uint ## __type_size ## _t val = VAL ## __type_size;		\
+		uint ## __type_size ## _t *ptr = (uint ## __type_size ## _t *) (buf + offset); \
+		memcpy(ptr, &val, sizeof(val));					\
+		val = test_ ## __inst(ptr, offset, val);			\
+		EXPECT_EQ(VAL ## __type_size, val);				\
+	}									\
+}

WARNING: Prefer __aligned(16) over __attribute__((aligned(16)))
#510: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:115:
+	uint8_t buf[16] __attribute__((aligned(16)));				\

CHECK: spaces preferred around that '*' (ctx:WxV)
#517: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:122:
+		uint ## __type_size ## _t *ptr = (uint ## __type_size ## _t *) (buf + offset); \
 		                          ^

ERROR: Macros with complex values should be enclosed in parentheses
#535: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:140:
+#define TEST_GP_STORE(__inst, __type_size)					\
+TEST(gp_load_ ## __inst)							\
+{										\
+	int offset, ret;							\
+	uint8_t buf[16] __attribute__((aligned(16)));				\
+										\
+	ret = prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT);			\
+	ASSERT_EQ(ret, 0);							\
+										\
+	for (offset = 1; offset < __type_size / 8; offset++) {			\
+		uint ## __type_size ## _t val = VAL ## __type_size;		\
+		uint ## __type_size ## _t *ptr = (uint ## __type_size ## _t *) (buf + offset); \
+		memset(ptr, 0, sizeof(val));					\
+		test_ ## __inst(ptr, offset, val);				\
+		memcpy(&val, ptr, sizeof(val));					\
+		EXPECT_EQ(VAL ## __type_size, val);				\
+	}									\
+}

CHECK: Macro argument '__type_size' may be better as '(__type_size)' to avoid precedence issues
#535: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:140:
+#define TEST_GP_STORE(__inst, __type_size)					\
+TEST(gp_load_ ## __inst)							\
+{										\
+	int offset, ret;							\
+	uint8_t buf[16] __attribute__((aligned(16)));				\
+										\
+	ret = prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT);			\
+	ASSERT_EQ(ret, 0);							\
+										\
+	for (offset = 1; offset < __type_size / 8; offset++) {			\
+		uint ## __type_size ## _t val = VAL ## __type_size;		\
+		uint ## __type_size ## _t *ptr = (uint ## __type_size ## _t *) (buf + offset); \
+		memset(ptr, 0, sizeof(val));					\
+		test_ ## __inst(ptr, offset, val);				\
+		memcpy(&val, ptr, sizeof(val));					\
+		EXPECT_EQ(VAL ## __type_size, val);				\
+	}									\
+}

WARNING: Prefer __aligned(16) over __attribute__((aligned(16)))
#539: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:144:
+	uint8_t buf[16] __attribute__((aligned(16)));				\

CHECK: spaces preferred around that '*' (ctx:WxV)
#546: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:151:
+		uint ## __type_size ## _t *ptr = (uint ## __type_size ## _t *) (buf + offset); \
 		                          ^

CHECK: Please use a blank line after function/struct/union/enum declarations
#553: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:158:
+}
+TEST_GP_STORE(sh, 16);

ERROR: Macros with complex values should be enclosed in parentheses
#562: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:167:
+#define __TEST_FPU_LOAD(__type, __inst, __reg_start, __reg_end)			\
+TEST(fpu_load_ ## __inst)							\
+{										\
+	int i, ret, offset, fp_reg;						\
+	uint8_t buf[16] __attribute__((aligned(16)));				\
+										\
+	ret = prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT);			\
+	ASSERT_EQ(ret, 0);							\
+										\
+	for (fp_reg = __reg_start; fp_reg < __reg_end; fp_reg++) {		\
+		for (offset = 1; offset < 4; offset++) {			\
+			void *load_addr = (buf + offset);			\
+			__type val = VAL_ ## __type ;				\
+										\
+			memcpy(load_addr, &val, sizeof(val));			\
+			val = test_ ## __inst(fp_reg, load_addr, offset, val);	\
+			EXPECT_TRUE(__type ##_equal(val, VAL_## __type));	\
+		}								\
+	}									\
+}

CHECK: Macro argument '__reg_end' may be better as '(__reg_end)' to avoid precedence issues
#562: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:167:
+#define __TEST_FPU_LOAD(__type, __inst, __reg_start, __reg_end)			\
+TEST(fpu_load_ ## __inst)							\
+{										\
+	int i, ret, offset, fp_reg;						\
+	uint8_t buf[16] __attribute__((aligned(16)));				\
+										\
+	ret = prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT);			\
+	ASSERT_EQ(ret, 0);							\
+										\
+	for (fp_reg = __reg_start; fp_reg < __reg_end; fp_reg++) {		\
+		for (offset = 1; offset < 4; offset++) {			\
+			void *load_addr = (buf + offset);			\
+			__type val = VAL_ ## __type ;				\
+										\
+			memcpy(load_addr, &val, sizeof(val));			\
+			val = test_ ## __inst(fp_reg, load_addr, offset, val);	\
+			EXPECT_TRUE(__type ##_equal(val, VAL_## __type));	\
+		}								\
+	}									\
+}

WARNING: Prefer __aligned(16) over __attribute__((aligned(16)))
#566: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:171:
+	uint8_t buf[16] __attribute__((aligned(16)));				\

CHECK: Please use a blank line after function/struct/union/enum declarations
#582: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:187:
+}
+#define TEST_FPU_LOAD(__type, __inst) \

ERROR: Macros with complex values should be enclosed in parentheses
#594: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:199:
+#define __TEST_FPU_STORE(__type, __inst, __reg_start, __reg_end)		\
+TEST(fpu_store_ ## __inst)							\
+{										\
+	int i, ret, offset, fp_reg;						\
+	uint8_t buf[16] __attribute__((aligned(16)));				\
+										\
+	ret = prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT);			\
+	ASSERT_EQ(ret, 0);							\
+										\
+	for (fp_reg = __reg_start; fp_reg < __reg_end; fp_reg++) {		\
+		for (offset = 1; offset < 4; offset++) {			\
+										\
+			void *store_addr = (buf + offset);			\
+			__type val = VAL_ ## __type ;				\
+										\
+			test_ ## __inst(fp_reg, store_addr, offset, val);	\
+			memcpy(&val, store_addr, sizeof(val));			\
+			EXPECT_TRUE(__type ## _equal(val, VAL_## __type));	\
+		}								\
+	}									\
+}

CHECK: Macro argument '__reg_end' may be better as '(__reg_end)' to avoid precedence issues
#594: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:199:
+#define __TEST_FPU_STORE(__type, __inst, __reg_start, __reg_end)		\
+TEST(fpu_store_ ## __inst)							\
+{										\
+	int i, ret, offset, fp_reg;						\
+	uint8_t buf[16] __attribute__((aligned(16)));				\
+										\
+	ret = prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT);			\
+	ASSERT_EQ(ret, 0);							\
+										\
+	for (fp_reg = __reg_start; fp_reg < __reg_end; fp_reg++) {		\
+		for (offset = 1; offset < 4; offset++) {			\
+										\
+			void *store_addr = (buf + offset);			\
+			__type val = VAL_ ## __type ;				\
+										\
+			test_ ## __inst(fp_reg, store_addr, offset, val);	\
+			memcpy(&val, store_addr, sizeof(val));			\
+			EXPECT_TRUE(__type ## _equal(val, VAL_## __type));	\
+		}								\
+	}									\
+}

WARNING: Prefer __aligned(16) over __attribute__((aligned(16)))
#598: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:203:
+	uint8_t buf[16] __attribute__((aligned(16)));				\

CHECK: Please use a blank line after function/struct/union/enum declarations
#615: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:220:
+}
+#define TEST_FPU_STORE(__type, __inst) \

WARNING: Prefer __aligned(16) over __attribute__((aligned(16)))
#630: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:235:
+	uint8_t buf[16] __attribute__((aligned(16)));

total: 6 errors, 10 warnings, 9 checks, 583 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit efdc802d7bbe ("selftests: riscv: add misaligned access testing") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
CHECK: Macro argument '__reg_end' may be better as '(__reg_end)' to avoid precedence issues
CHECK: Macro argument '__type_size' may be better as '(__type_size)' to avoid precedence issues
CHECK: Please use a blank line after function/struct/union/enum declarations
CHECK: spaces preferred around that '*' (ctx:WxV)
ERROR: Macros with complex values should be enclosed in parentheses
WARNING: 'ment' may be misspelled - perhaps 'meant'?
WARNING: Prefer __aligned(16) over __attribute__((aligned(16)))
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?

linux-riscv-bot · 2025-04-22T23:37:12Z

Patch 5: "[v2,5/5] selftests: riscv: add misaligned access testing"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 39.69 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T23:37:14Z

Patch 5: "[v2,5/5] selftests: riscv: add misaligned access testing"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.22 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T23:37:16Z

Patch 5: "[v2,5/5] selftests: riscv: add misaligned access testing"
kdoc
Desc: Detects for kdoc errors
Duration: 0.85 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T23:37:18Z

Patch 5: "[v2,5/5] selftests: riscv: add misaligned access testing"
module-param
Desc: Detect module_param changes
Duration: 0.24 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T23:37:20Z

Patch 5: "[v2,5/5] selftests: riscv: add misaligned access testing"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.22 seconds
Result: PASS

linux-riscv-bot · 2025-04-22T23:37:22Z

Patch 5: "[v2,5/5] selftests: riscv: add misaligned access testing"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.29 seconds
Result: PASS

Linux RISC-V bot and others added 6 commits April 16, 2025 18:23

Adding CI files

6c2725a

linux-riscv-bot force-pushed the workflow__riscv__fixes branch from 6c2725a to c8da138 Compare April 24, 2025 20:46

linux-riscv-bot closed this Apr 30, 2025

linux-riscv-bot deleted the pw955846 branch April 30, 2025 01:03

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