[PW_SID:958418] RISC-V KVM selftests improvements#358
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The current exeception register structure in selftests are missing few registers (e.g stval). Instead of adding it manually, change the ex_regs to align with pt_regs to make it future proof. Suggested-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Currently, the sbi_pmu_test continues if the exception type is illegal instruction because access to hpmcounter will generate that. However illegal instruction exception may occur due to the other reasons which should result in test assertion. Use the stval to decode the exact type of instructions and which csrs are being accessed if it is csr access instructions. Assert in all cases except if it is a csr access instructions that access valid PMU related registers. Take this opportunity to remove the CSR_CYCLEH reference as the test is compiled for RV64 only. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add vector related tests with the ISA extension standard template. However, the vector registers are bit tricky as the register length is variable based on vlenb value of the system. That's why the macros are defined with a default and overidden with actual value at runtime. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v3,1/3] KVM: riscv: selftests: Align the trap information wiht pt_regs" |
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Patch 1: "[v3,1/3] KVM: riscv: selftests: Align the trap information wiht pt_regs" |
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Patch 1: "[v3,1/3] KVM: riscv: selftests: Align the trap information wiht pt_regs" |
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Patch 1: "[v3,1/3] KVM: riscv: selftests: Align the trap information wiht pt_regs" |
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Patch 1: "[v3,1/3] KVM: riscv: selftests: Align the trap information wiht pt_regs" |
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Patch 1: "[v3,1/3] KVM: riscv: selftests: Align the trap information wiht pt_regs" |
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Patch 1: "[v3,1/3] KVM: riscv: selftests: Align the trap information wiht pt_regs" |
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Patch 1: "[v3,1/3] KVM: riscv: selftests: Align the trap information wiht pt_regs" |
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Patch 1: "[v3,1/3] KVM: riscv: selftests: Align the trap information wiht pt_regs" |
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Patch 1: "[v3,1/3] KVM: riscv: selftests: Align the trap information wiht pt_regs" |
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Patch 1: "[v3,1/3] KVM: riscv: selftests: Align the trap information wiht pt_regs" |
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Patch 1: "[v3,1/3] KVM: riscv: selftests: Align the trap information wiht pt_regs" |
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Patch 2: "[v3,2/3] KVM: riscv: selftests: Decode stval to identify exact exception type" |
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Patch 2: "[v3,2/3] KVM: riscv: selftests: Decode stval to identify exact exception type" |
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Patch 2: "[v3,2/3] KVM: riscv: selftests: Decode stval to identify exact exception type" |
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Patch 2: "[v3,2/3] KVM: riscv: selftests: Decode stval to identify exact exception type" |
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Patch 2: "[v3,2/3] KVM: riscv: selftests: Decode stval to identify exact exception type" |
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Patch 2: "[v3,2/3] KVM: riscv: selftests: Decode stval to identify exact exception type" |
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Patch 2: "[v3,2/3] KVM: riscv: selftests: Decode stval to identify exact exception type" |
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Patch 2: "[v3,2/3] KVM: riscv: selftests: Decode stval to identify exact exception type" |
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Patch 2: "[v3,2/3] KVM: riscv: selftests: Decode stval to identify exact exception type" |
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Patch 2: "[v3,2/3] KVM: riscv: selftests: Decode stval to identify exact exception type" |
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Patch 2: "[v3,2/3] KVM: riscv: selftests: Decode stval to identify exact exception type" |
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Patch 2: "[v3,2/3] KVM: riscv: selftests: Decode stval to identify exact exception type" |
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Patch 3: "[v3,3/3] KVM: riscv: selftests: Add vector extension tests" |
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Patch 3: "[v3,3/3] KVM: riscv: selftests: Add vector extension tests" |
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Patch 3: "[v3,3/3] KVM: riscv: selftests: Add vector extension tests" |
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Patch 3: "[v3,3/3] KVM: riscv: selftests: Add vector extension tests" |
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Patch 3: "[v3,3/3] KVM: riscv: selftests: Add vector extension tests" |
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Patch 3: "[v3,3/3] KVM: riscv: selftests: Add vector extension tests" |
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Patch 3: "[v3,3/3] KVM: riscv: selftests: Add vector extension tests" |
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Patch 3: "[v3,3/3] KVM: riscv: selftests: Add vector extension tests" |
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Patch 3: "[v3,3/3] KVM: riscv: selftests: Add vector extension tests" |
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Patch 3: "[v3,3/3] KVM: riscv: selftests: Add vector extension tests" |
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Patch 3: "[v3,3/3] KVM: riscv: selftests: Add vector extension tests" |
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Patch 3: "[v3,3/3] KVM: riscv: selftests: Add vector extension tests" |
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PR for series 958418 applied to workflow__riscv__fixes
Name: RISC-V KVM selftests improvements
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=958418
Version: 3