[PW_SID:959342] add Voyager board support#370
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The first SoC in the Andes series is QiLai. It includes a high-performance quad-core RISC-V AX45MP cluster and one NX27V vector processor. For further information, refer to [1]. [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/ Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add DT binding documentation for the Andes QiLai SoC and the Voyager development board. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add a new compatible string for Andes QiLai PLIC. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
…nterrupt controller Add the DT binding documentation for Andes machine-level software interrupt controller. In the Andes platform such as QiLai SoC, the PLIC module is instantiated a second time with all interrupt sources tied to zero as the software interrupt controller (PLICSW). PLICSW can generate machine-level software interrupts through programming its registers. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add the DT binding documentation for Andes machine timer. The RISC-V architecture defines a machine timer that provides a real-time counter and generates timer interrupts. Andes machiner timer (PLMT0) is the implementation of the machine timer, and it contains memory-mapped registers (mtime and mtimecmp). This device supports up to 32 cores. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
… L2 cache The current device tree binding for the Andes AX45MP L2 cache enforces a fixed number of cache-sets (1024). However, there are 2048 cache-sets in the QiLai SoC. This change allows both 1024 and 2048 as valid values for "cache-sets". Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Introduce the initial device tree support for the Andes QiLai SoC. For further information, you can refer to [1]. [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/ Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Introduce the device tree support for Voyager development board. Currently only support booting into console with only uart, other features will be added later. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Enable Andes SoC config in defconfig to allow the default upstream kernel to boot on Voyager board. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v2,1/9] riscv: add Andes SoC family Kconfig support" |
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Patch 1: "[v2,1/9] riscv: add Andes SoC family Kconfig support" |
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Patch 1: "[v2,1/9] riscv: add Andes SoC family Kconfig support" |
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Patch 1: "[v2,1/9] riscv: add Andes SoC family Kconfig support" |
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Patch 1: "[v2,1/9] riscv: add Andes SoC family Kconfig support" |
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Patch 1: "[v2,1/9] riscv: add Andes SoC family Kconfig support" |
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Patch 1: "[v2,1/9] riscv: add Andes SoC family Kconfig support" |
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Patch 1: "[v2,1/9] riscv: add Andes SoC family Kconfig support" |
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Patch 1: "[v2,1/9] riscv: add Andes SoC family Kconfig support" |
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Patch 1: "[v2,1/9] riscv: add Andes SoC family Kconfig support" |
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Patch 1: "[v2,1/9] riscv: add Andes SoC family Kconfig support" |
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Patch 1: "[v2,1/9] riscv: add Andes SoC family Kconfig support" |
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Patch 2: "[v2,2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings" |
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Patch 2: "[v2,2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings" |
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Patch 2: "[v2,2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings" |
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Patch 2: "[v2,2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings" |
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Patch 2: "[v2,2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings" |
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Patch 2: "[v2,2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings" |
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Patch 2: "[v2,2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings" |
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Patch 2: "[v2,2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings" |
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Patch 7: "[v2,7/9] riscv: dts: andes: add QiLai SoC device tree" |
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Patch 7: "[v2,7/9] riscv: dts: andes: add QiLai SoC device tree" |
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Patch 8: "[v2,8/9] riscv: dts: andes: add Voyager board device tree" |
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Patch 8: "[v2,8/9] riscv: dts: andes: add Voyager board device tree" |
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Patch 8: "[v2,8/9] riscv: dts: andes: add Voyager board device tree" |
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Patch 8: "[v2,8/9] riscv: dts: andes: add Voyager board device tree" |
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Patch 8: "[v2,8/9] riscv: dts: andes: add Voyager board device tree" |
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Patch 8: "[v2,8/9] riscv: dts: andes: add Voyager board device tree" |
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Patch 8: "[v2,8/9] riscv: dts: andes: add Voyager board device tree" |
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Patch 8: "[v2,8/9] riscv: dts: andes: add Voyager board device tree" |
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Patch 8: "[v2,8/9] riscv: dts: andes: add Voyager board device tree" |
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Patch 8: "[v2,8/9] riscv: dts: andes: add Voyager board device tree" |
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Patch 8: "[v2,8/9] riscv: dts: andes: add Voyager board device tree" |
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Patch 8: "[v2,8/9] riscv: dts: andes: add Voyager board device tree" |
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Patch 9: "[v2,9/9] riscv: defconfig: enable Andes SoC" |
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Patch 9: "[v2,9/9] riscv: defconfig: enable Andes SoC" |
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Patch 9: "[v2,9/9] riscv: defconfig: enable Andes SoC" |
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Patch 9: "[v2,9/9] riscv: defconfig: enable Andes SoC" |
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Patch 9: "[v2,9/9] riscv: defconfig: enable Andes SoC" |
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Patch 9: "[v2,9/9] riscv: defconfig: enable Andes SoC" |
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Patch 9: "[v2,9/9] riscv: defconfig: enable Andes SoC" |
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Patch 9: "[v2,9/9] riscv: defconfig: enable Andes SoC" |
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Patch 9: "[v2,9/9] riscv: defconfig: enable Andes SoC" |
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Patch 9: "[v2,9/9] riscv: defconfig: enable Andes SoC" |
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Patch 9: "[v2,9/9] riscv: defconfig: enable Andes SoC" |
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Patch 9: "[v2,9/9] riscv: defconfig: enable Andes SoC" |
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PR for series 959342 applied to workflow__riscv__fixes
Name: add Voyager board support
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=959342
Version: 2