[PW_SID:959792] Enable hstateen bits lazily for the KVM RISC-V Guests#377
[PW_SID:959792] Enable hstateen bits lazily for the KVM RISC-V Guests#377linux-riscv-bot wants to merge 6 commits into
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Currently, we enable the smstateen bit at vcpu configure time by only checking the presence of required ISA extensions. These bits are not required to be enabled if the guest never uses the corresponding architectural state. Enable the smstaeen bits at runtime lazily upon first access. Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Hstateen has different bits that can be enabled lazily at runtime. Most of them have similar functionality where the hstateen bit must be enabled if not enabled already. The correpsonding config bit in vcpu must be enabled as well so that hstateen CSR is updated correctly during the next vcpu load. In absesnce of Smstateen extension, exit to the userspace in the trap because CSR access control exists architecturally only if Smstateen extension is available. Add a common helper function to achieve the above said objective. Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Smstateen extension controls the SISELECT and SIPH/SIEH register through hstateen.AIA bit (58). Add lazy enabling support for those bits. Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
SENVCFG and SSTATEEN CSRs are controlled by HSENVCFG(62) and SSTATEEN0(63) bits in hstateen. Enable them lazily at runtime instead of bootime. Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
All the existing hstateen bits can be enabled at runtime upon first access now. Remove the default enabling at bootime now. Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit" |
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Patch 1: "[1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit" |
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Patch 1: "[1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit" |
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Patch 1: "[1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit" |
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Patch 1: "[1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit" |
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Patch 1: "[1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit" |
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Patch 1: "[1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit" |
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Patch 1: "[1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit" |
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Patch 1: "[1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit" |
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Patch 1: "[1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit" |
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Patch 1: "[1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit" |
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Patch 1: "[1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit" |
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Patch 2: "[2/5] RISC-V: KVM: Add a hstateen lazy enabler helper function" |
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Patch 2: "[2/5] RISC-V: KVM: Add a hstateen lazy enabler helper function" |
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Patch 2: "[2/5] RISC-V: KVM: Add a hstateen lazy enabler helper function" |
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Patch 2: "[2/5] RISC-V: KVM: Add a hstateen lazy enabler helper function" |
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Patch 2: "[2/5] RISC-V: KVM: Add a hstateen lazy enabler helper function" |
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Patch 2: "[2/5] RISC-V: KVM: Add a hstateen lazy enabler helper function" |
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Patch 2: "[2/5] RISC-V: KVM: Add a hstateen lazy enabler helper function" |
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Patch 2: "[2/5] RISC-V: KVM: Add a hstateen lazy enabler helper function" |
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Patch 2: "[2/5] RISC-V: KVM: Add a hstateen lazy enabler helper function" |
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Patch 2: "[2/5] RISC-V: KVM: Add a hstateen lazy enabler helper function" |
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Patch 2: "[2/5] RISC-V: KVM: Add a hstateen lazy enabler helper function" |
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Patch 2: "[2/5] RISC-V: KVM: Add a hstateen lazy enabler helper function" |
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Patch 3: "[3/5] RISC-V: KVM: Support lazy enabling of siselect and aia bits" |
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Patch 3: "[3/5] RISC-V: KVM: Support lazy enabling of siselect and aia bits" |
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Patch 3: "[3/5] RISC-V: KVM: Support lazy enabling of siselect and aia bits" |
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Patch 4: "[4/5] RISC-V: KVM: Enable envcfg and sstateen bits lazily" |
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Patch 4: "[4/5] RISC-V: KVM: Enable envcfg and sstateen bits lazily" |
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Patch 4: "[4/5] RISC-V: KVM: Enable envcfg and sstateen bits lazily" |
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Patch 4: "[4/5] RISC-V: KVM: Enable envcfg and sstateen bits lazily" |
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Patch 4: "[4/5] RISC-V: KVM: Enable envcfg and sstateen bits lazily" |
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Patch 4: "[4/5] RISC-V: KVM: Enable envcfg and sstateen bits lazily" |
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Patch 4: "[4/5] RISC-V: KVM: Enable envcfg and sstateen bits lazily" |
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Patch 4: "[4/5] RISC-V: KVM: Enable envcfg and sstateen bits lazily" |
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Patch 4: "[4/5] RISC-V: KVM: Enable envcfg and sstateen bits lazily" |
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Patch 4: "[4/5] RISC-V: KVM: Enable envcfg and sstateen bits lazily" |
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Patch 4: "[4/5] RISC-V: KVM: Enable envcfg and sstateen bits lazily" |
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Patch 4: "[4/5] RISC-V: KVM: Enable envcfg and sstateen bits lazily" |
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Patch 5: "[5/5] RISC-V: KVM: Remove the boot time enabling of hstateen bits" |
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Patch 5: "[5/5] RISC-V: KVM: Remove the boot time enabling of hstateen bits" |
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Patch 5: "[5/5] RISC-V: KVM: Remove the boot time enabling of hstateen bits" |
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Patch 5: "[5/5] RISC-V: KVM: Remove the boot time enabling of hstateen bits" |
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Patch 5: "[5/5] RISC-V: KVM: Remove the boot time enabling of hstateen bits" |
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Patch 5: "[5/5] RISC-V: KVM: Remove the boot time enabling of hstateen bits" |
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Patch 5: "[5/5] RISC-V: KVM: Remove the boot time enabling of hstateen bits" |
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Patch 5: "[5/5] RISC-V: KVM: Remove the boot time enabling of hstateen bits" |
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Patch 5: "[5/5] RISC-V: KVM: Remove the boot time enabling of hstateen bits" |
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Patch 5: "[5/5] RISC-V: KVM: Remove the boot time enabling of hstateen bits" |
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Patch 5: "[5/5] RISC-V: KVM: Remove the boot time enabling of hstateen bits" |
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Patch 5: "[5/5] RISC-V: KVM: Remove the boot time enabling of hstateen bits" |
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PR for series 959792 applied to workflow__riscv__fixes
Name: Enable hstateen bits lazily for the KVM RISC-V Guests
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=959792
Version: 1