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eb16b37
riscv: misaligned: Add handling for ZCB instructions
nylon7 Apr 11, 2025
23d099a
riscv: misaligned: factorize trap handling
clementleger Apr 22, 2025
8786815
riscv: misaligned: enable IRQs while handling misaligned accesses
clementleger Apr 22, 2025
6f1ddb7
riscv: misaligned: use get_user() instead of __get_user()
clementleger Apr 22, 2025
81de1af
riscv: Fix kernel crash due to PR_SET_TAGGED_ADDR_CTRL
covanam May 4, 2025
b72da57
scripts: Do not strip .rela.dyn section
Apr 8, 2025
33bf768
riscv: ftrace: support fastcc in Clang for WITH_ARGS
AndybnACT Apr 7, 2025
c2509cf
riscv: ftrace factor out code defined by !WITH_ARG
AndybnACT Apr 7, 2025
de482ee
riscv: save the SR_SUM status over switches
bjdooks-ct Apr 10, 2025
abd5987
riscv: ftrace: align patchable functions to 4 Byte boundary
AndybnACT Apr 7, 2025
16d7285
riscv: implement user_access_begin() and families
xhackerustc Apr 10, 2025
0afc687
kernel: ftrace: export ftrace_sync_ipi
AndybnACT Apr 7, 2025
b7f56b9
riscv: uaccess: use input constraints for ptr of __put_user()
xhackerustc Apr 10, 2025
ec10ec6
riscv: ftrace: prepare ftrace for atomic code patching
AndybnACT Apr 7, 2025
9f4dd8c
riscv: uaccess: use 'asm goto' for put_user()
xhackerustc Apr 10, 2025
224924b
riscv: ftrace: do not use stop_machine to update code
AndybnACT Apr 7, 2025
ed5d6b9
riscv: uaccess: use 'asm_goto_output' for get_user()
xhackerustc Apr 10, 2025
7b0f441
riscv: vector: Support calling schedule() for preemptible Vector
AndybnACT Apr 7, 2025
39e7f74
riscv: add a data fence for CMODX in the kernel mode
AndybnACT Apr 7, 2025
ecca5b0
riscv: ftrace: support PREEMPT
AndybnACT Apr 7, 2025
fd3a21f
riscv: Implement HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS
puranjaymohan Apr 7, 2025
f3977de
riscv: Introduce Zicbop instructions
Apr 21, 2025
f4b8329
riscv: ftrace: support direct call using call_ops
AndybnACT Apr 7, 2025
24b68b3
riscv: Add support for Zicbop
Apr 21, 2025
98d01fe
riscv: kexec_file: Split the loading of kernel and others
Apr 9, 2025
1aefa6c
riscv/kexec_file: Fix comment in purgatory relocator
ziyao233 Mar 26, 2025
af0498d
riscv: Documentation: add a description about dynamic ftrace
AndybnACT Apr 7, 2025
ebf8a10
riscv: Add ARCH_HAS_PREFETCH[W] support with Zicbop
guoren83 Apr 21, 2025
6a8666e
riscv: kexec_file: Support loading Image binary file
Apr 9, 2025
0778d30
riscv: Add support for PUD THP
Mar 21, 2025
088a8ca
Merge patch series "riscv: uaccess: optimisations"
Apr 22, 2025
d8fa7ee
Merge patch series "riscv: ftrace: atmoic patching and preempt improv…
Apr 22, 2025
324810c
riscv: module: Optimize PLT/GOT entry counting
SiFiveHolland Apr 9, 2025
fe5dbee
RISC-V: Kconfig: Fix help text of CMDLINE_EXTEND
Red54 Mar 28, 2025
a2711b0
riscv: xchg: Prefetch the destination word for sc.w
guoren83 Apr 21, 2025
589a275
Merge patch series "riscv: kexec_file: Support loading Image binary f…
May 6, 2025
d4bed96
perf symbols: Ignore mapping symbols on riscv
xiaobo55x Apr 9, 2025
ad8367b
riscv: Make regs_irqs_disabled() more clear
seehearfeel Apr 22, 2025
7c30767
riscv: hwprobe: export Zabha extension
Apr 21, 2025
c5385c4
Merge patch series "riscv: Add Zicbop & prefetchw support"
May 6, 2025
466c1a8
MAINTAINERS: Update Atish's email address
atishp04 May 5, 2025
25185c6
riscv: Improve Kconfig help for RISCV_ISA_V_PREEMPTIVE
mssola May 1, 2025
e3c23da
Documentation/sysctl: add riscv to unaligned-trap supported archs
clementleger Apr 22, 2025
15deee8
selftests: riscv: add misaligned access testing
clementleger Apr 22, 2025
eff5177
riscv: sbi: add Firmware Feature (FWFT) SBI extensions definitions
clementleger Apr 24, 2025
ef11a9a
riscv: sbi: remove useless parenthesis
clementleger Apr 24, 2025
c8b8d19
riscv: sbi: add new SBI error mappings
clementleger Apr 24, 2025
af43847
riscv: sbi: add FWFT extension interface
clementleger Apr 24, 2025
b65362c
riscv: sbi: add SBI FWFT extension calls
clementleger Apr 24, 2025
8d27ed1
riscv: misaligned: request misaligned exception from SBI
clementleger Apr 24, 2025
f11ec5d
riscv: misaligned: use on_each_cpu() for scalar misaligned access pro…
clementleger Apr 24, 2025
fc241d0
riscv: misaligned: use correct CONFIG_ ifdef for misaligned_access_speed
clementleger Apr 24, 2025
0046a37
riscv: misaligned: move emulated access uniformity check in a function
clementleger Apr 24, 2025
66a77b1
riscv: misaligned: add a function to check misalign trap delegability
clementleger Apr 24, 2025
1ff07ab
RISC-V: KVM: add SBI extension init()/deinit() functions
clementleger Apr 24, 2025
1bd16c2
RISC-V: KVM: add SBI extension reset callback
clementleger Apr 24, 2025
48d8aa4
RISC-V: KVM: add support for FWFT SBI extension
clementleger Apr 24, 2025
cc70a8c
RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG
clementleger Apr 24, 2025
fa08d32
Merge patch series "riscv: add SBI FWFT misaligned exception delegati…
May 6, 2025
69c013a
mm: VM_SHADOW_STACK definition for riscv
deepak0414 May 2, 2025
91b18be
dt-bindings: riscv: zicfilp and zicfiss in dt-bindings (extensions.yaml)
deepak0414 May 2, 2025
850f8f0
riscv: zicfiss / zicfilp enumeration
deepak0414 May 2, 2025
6fb8473
riscv: zicfiss / zicfilp extension csr and bit definitions
deepak0414 May 2, 2025
85e2a2d
riscv: usercfi state for task and save/restore of CSR_SSP on trap ent…
deepak0414 May 2, 2025
6ec64b8
riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE
deepak0414 May 2, 2025
99a6f73
riscv mm: manufacture shadow stack pte
deepak0414 May 2, 2025
6fd11bc
riscv mmu: teach pte_mkwrite to manufacture shadow stack PTEs
deepak0414 May 2, 2025
61b80a4
riscv mmu: write protect and shadow stack
deepak0414 May 2, 2025
4a39b38
riscv/mm: Implement map_shadow_stack() syscall
deepak0414 May 2, 2025
3db2d5e
riscv/shstk: If needed allocate a new shadow stack on clone
deepak0414 May 2, 2025
8ebd0a4
riscv: Implements arch agnostic shadow stack prctls
deepak0414 May 2, 2025
0c62a3b
prctl: arch-agnostic prctl for indirect branch tracking
deepak0414 May 2, 2025
1327cff
riscv: Implements arch agnostic indirect branch tracking prctls
deepak0414 May 2, 2025
c82bada
riscv/traps: Introduce software check exception
deepak0414 May 2, 2025
b5a058e
riscv: signal: abstract header saving for setup_sigcontext
AndybnACT May 2, 2025
a4fa9c9
riscv/signal: save and restore of shadow stack for signal
deepak0414 May 2, 2025
71117d7
riscv/kernel: update __show_regs to print shadow stack register
deepak0414 May 2, 2025
65d9bb2
riscv/ptrace: riscv cfi status and state via ptrace and in core files
deepak0414 May 2, 2025
c6fb2eb
riscv/hwprobe: zicfilp / zicfiss enumeration in hwprobe
deepak0414 May 2, 2025
3190a7d
riscv: kernel command line option to opt out of user cfi
deepak0414 May 2, 2025
47c129a
riscv: enable kernel access to shadow stack memory via FWFT sbi call
deepak0414 May 2, 2025
1563351
arch/riscv: compile vdso with landing pad
cwshu May 2, 2025
47b0947
riscv: create a config for shadow stack and landing pad instr support
deepak0414 May 2, 2025
ffdeac6
riscv: Documentation for landing pad / indirect branch tracking
deepak0414 May 2, 2025
9187428
riscv: Documentation for shadow stack on riscv
deepak0414 May 2, 2025
2eef70b
kselftest/riscv: kselftest for user mode cfi
deepak0414 May 2, 2025
9e7d4d4
Merge patch series "riscv control-flow integrity for usermode"
May 6, 2025
a896329
drivers/perf: riscv: Add SBI v3.0 flag
atishp04 Jan 15, 2025
2c88828
drivers/perf: riscv: Add raw event v2 support
atishp04 Jan 15, 2025
b858a72
RISC-V: KVM: Add support for Raw event v2
atishp04 Jan 15, 2025
c708803
drivers/perf: riscv: Implement PMU event info function
atishp04 Jan 15, 2025
ad956fa
drivers/perf: riscv: Export PMU event info function
atishp04 Jan 15, 2025
eb15b56
KVM: Add a helper function to validate vcpu gpa range
atishp04 Jan 15, 2025
5e638ec
RISC-V: KVM: Use the new gpa range validate helper function
atishp04 Jan 15, 2025
3601a57
RISC-V: KVM: Implement get event info function
atishp04 Jan 15, 2025
064667e
RISC-V: KVM: Upgrade the supported SBI version to 3.0
atishp04 Jan 15, 2025
f478bb7
Merge patch series "Add SBI v3.0 PMU enhancements"
May 6, 2025
eed0791
Adding CI files
May 6, 2025
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Binary file added .github/.MISSING_LINARO_DEP.swp
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Binary file added .github/.swp
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11 changes: 11 additions & 0 deletions .github/MISSING_LINARO_DEP
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
gdb (ltp vma05)
libnuma (ltp vma02-4)
swap file (swapping01)
fusermount (run_fuse_test.sh)
libfuse (run_fuse_test.sh)
mkisofs genisoimage xorrisofs (isofs.sh)
all modules (binfmt_misc0X)
mksquashfs
LTP_TIMEOUT_MUL > 1 (starvation)
libubsan ()
XXX (ltp-aiodio MUST be added)
Binary file added .github/scripts/.patches.sh.swp
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31 changes: 31 additions & 0 deletions .github/scripts/build_ubuntu_defconfig.sh
Original file line number Diff line number Diff line change
@@ -0,0 +1,31 @@
#!/bin/bash
# SPDX-FileCopyrightText: 2024 Rivos Inc.
#
# SPDX-License-Identifier: Apache-2.0

set -euox pipefail
d=$(dirname "${BASH_SOURCE[0]}")
. $d/series/utils.sh

logs=$(get_logs_dir)
f=${logs}/build_ubuntu_defconfig.log

date -Iseconds | tee -a ${f}
echo "Build an ubuntu kernel" | tee -a ${f}
echo "Top 16 commits" | tee -a ${f}
git log -16 --abbrev=12 --pretty="commit %h (\"%s\")" | tee -a ${f}

kernel_base_sha=$(git log -1 --pretty=%H $(git log -1 --reverse --pretty=%H .github)^)
echo "build_name $(git describe --tags ${kernel_base_sha})" | tee -a ${f}
build_name=$(git describe --tags ${kernel_base_sha})

# Build the kernel that will run LTP
export CI_TRIPLE="riscv64-unknown-linux-gnu"
# Use a CFI-enabled toolchain
export PATH=/build/INSTALL_Sept24/bin:$PATH
cp $d/series/kconfigs/ubuntu_defconfig arch/riscv/configs/
$d/series/kernel_builder.sh rv64 testsuites plain gcc | tee -a ${f}

kernel_dir="/build/$(gen_kernel_name rv64 testsuites plain gcc)"
echo $build_name > $kernel_dir/kernel_version
#tar cJvf --exclude $(basename $kernel_path) modules.tar.xz /build/$(gen_kernel_name rv64 testsuites plain gcc)/
2 changes: 2 additions & 0 deletions .github/scripts/ci/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@
from .base import Base, EndTest, Verdict, submit_pw_check
from .shelltest import ShellTest
120 changes: 120 additions & 0 deletions .github/scripts/ci/base.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,120 @@
from abc import ABC, abstractmethod
from enum import Enum
import time
import sys

from libs import utils

sys.path.insert(0, '../libs')
from libs import log_debug

class Verdict(Enum):
PENDING = 0
PASS = 1
FAIL = 2
ERROR = 3
SKIP = 4
WARNING = 5


class EndTest(Exception):
"""
End of Test
"""

class Base(ABC):
"""
Base class for CI Tests.
"""
def __init__(self):
self.start_time = 0
self.end_time = 0
self.verdict = Verdict.PENDING
self.output = ""

def success(self):
self.end_timer()
self.verdict = Verdict.PASS

def error(self, msg):
self.verdict = Verdict.ERROR
self.output = msg
self.end_timer()
raise EndTest

def warning(self, msg):
self.verdict = Verdict.WARNING
self.output = msg
self.end_timer()

def skip(self, msg):
self.verdict = Verdict.SKIP
self.output = msg
self.end_timer()
raise EndTest

def add_failure(self, msg):
self.verdict = Verdict.FAIL
if not self.output:
self.output = msg
else:
self.output += "\n" + msg

def add_failure_end_test(self, msg):
self.add_failure(msg)
self.end_timer()
raise EndTest

def start_timer(self):
self.start_time = time.time()

def end_timer(self):
self.end_time = time.time()

def elapsed(self):
if self.start_time == 0:
return 0
if self.end_time == 0:
self.end_timer()
return self.end_time - self.start_time

def log_err(self, msg):
utils.log_error(f"CI: {self.name}: {msg}")

def log_info(self, msg):
utils.log_info(f"CI: {self.name}: {msg}")

def log_dbg(self, msg):
utils.log_debug(f"CI: {self.name}: {msg}")

@abstractmethod
def run(self, worktree=None):
"""
The child class should implement run() method
If the test fail, it should raise the EndTest exception
"""
pass

@abstractmethod
def post_run(self):
"""
The child class should implement post_run() method
"""
pass


def submit_pw_check(pw, patch, name, verdict, desc, url=None, dry_run=False):

utils.log_debug(f"Submitting the result to PW: dry_run={dry_run}")

if not dry_run:
state = 0

if verdict == Verdict.PASS:
state = 1
if verdict == Verdict.WARNING:
state = 2
if verdict == Verdict.FAIL:
state = 3

pw.post_check(patch, name, state, desc, url)
67 changes: 67 additions & 0 deletions .github/scripts/ci/shelltest.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,67 @@
from gettext import install
import os
import sys

sys.path.insert(0, '../libs')
from libs import RepoTool, cmd_run

from ci import Base, Verdict, EndTest, submit_pw_check

class ShellTest(Base):
"""Run shell test class
This class runs a shell based test
"""

def __init__(self, ci_data, patch, name, desc, sh):

# Common
self.name = name
self.desc = desc
self.ci_data = ci_data

self.sh = sh
self.patch = patch

super().__init__()

self.log_dbg("Initialization completed")

def run(self, worktree=None):

self.log_dbg("Run")
self.start_timer()

current_script_path = os.path.dirname(os.path.abspath(__file__))

cwd = worktree if worktree else self.ci_data.src_dir
cmd = ["bash", f"{current_script_path}/../pw_tests/{self.sh}"]
(ret, stdout, stderr) = cmd_run(cmd, cwd=cwd)

if ret == 0:
submit_pw_check(self.ci_data.pw, self.patch,
self.name, Verdict.PASS,
self.name,
None, self.ci_data.config['dry_run'])
self.success()
elif ret == 250:
url = self.ci_data.gh.create_gist(f"pw{self.ci_data.series['id']}-p{self.patch['id']}",
f"{self.name}-WARNING",
stdout + '\n' + stderr)
submit_pw_check(self.ci_data.pw, self.patch,
self.name, Verdict.WARNING,
self.name,
url, self.ci_data.config['dry_run'])
self.warning(stdout + '\n' + stderr)
else:
url = self.ci_data.gh.create_gist(f"pw{self.ci_data.series['id']}-p{self.patch['id']}",
f"{self.name}-FAIL",
stdout + '\n' + stderr)
submit_pw_check(self.ci_data.pw, self.patch,
self.name, Verdict.FAIL,
self.name,
url, self.ci_data.config['dry_run'])
self.error(stdout + '\n' + stderr)

def post_run(self):

self.log_dbg("Post Run...")
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