[PW_SID:962682] RISC-V: KVM: Disable instret/cycle for VU mode by default#411
[PW_SID:962682] RISC-V: KVM: Disable instret/cycle for VU mode by default#411linux-riscv-bot wants to merge 2 commits into
Conversation
The KVM virtualizes PMU in RISC-V and disables all counter access except TM bit by default vi hstateen CSR. There is no benefit in enabling CY/TM bits in scounteren for the guest user space as it can't be run without hcounteren anyways. Allow only TM bit which matches the hcounteren default setting. Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
|
Patch 1: "RISC-V: KVM: Disable instret/cycle for VU mode by default" |
|
Patch 1: "RISC-V: KVM: Disable instret/cycle for VU mode by default" |
|
Patch 1: "RISC-V: KVM: Disable instret/cycle for VU mode by default" |
|
Patch 1: "RISC-V: KVM: Disable instret/cycle for VU mode by default" |
|
Patch 1: "RISC-V: KVM: Disable instret/cycle for VU mode by default" |
|
Patch 1: "RISC-V: KVM: Disable instret/cycle for VU mode by default" |
|
Patch 1: "RISC-V: KVM: Disable instret/cycle for VU mode by default" |
|
Patch 1: "RISC-V: KVM: Disable instret/cycle for VU mode by default" |
|
Patch 1: "RISC-V: KVM: Disable instret/cycle for VU mode by default" |
|
Patch 1: "RISC-V: KVM: Disable instret/cycle for VU mode by default" |
|
Patch 1: "RISC-V: KVM: Disable instret/cycle for VU mode by default" |
|
Patch 1: "RISC-V: KVM: Disable instret/cycle for VU mode by default" |
linux-riscv-bot
force-pushed
the
workflow__riscv__fixes
branch
2 times, most recently
from
de90874 to
400e3f8
Compare
2 participants
PR for series 962682 applied to workflow__riscv__fixes
Name: RISC-V: KVM: Disable instret/cycle for VU mode by default
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=962682
Version: 1