[PW_SID:962732] [v2] selftests: riscv: add misaligned access testing by linux-riscv-bot · Pull Request #412 · linux-riscv/linux

linux-riscv-bot · 2025-05-14T08:53:45Z

PR for series 962732 applied to workflow__riscv__fixes

Name: [v2] selftests: riscv: add misaligned access testing
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=962732
Version: 2

This selftest tests all the currently emulated instructions (except for the RV32 compressed ones which are left as a future exercise for a RV32 user). For the FPU instructions, all the FPU registers are tested. Signed-off-by: Clément Léger <cleger@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

linux-riscv-bot · 2025-05-14T08:58:55Z

Patch 1: "[v2] selftests: riscv: add misaligned access testing"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 105.90 seconds
Result: PASS

linux-riscv-bot · 2025-05-14T09:13:38Z

Patch 1: "[v2] selftests: riscv: add misaligned access testing"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 881.25 seconds
Result: PASS

linux-riscv-bot · 2025-05-14T09:32:44Z

Patch 1: "[v2] selftests: riscv: add misaligned access testing"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1144.12 seconds
Result: PASS

linux-riscv-bot · 2025-05-14T09:33:06Z

Patch 1: "[v2] selftests: riscv: add misaligned access testing"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 20.68 seconds
Result: PASS

linux-riscv-bot · 2025-05-14T09:33:29Z

Patch 1: "[v2] selftests: riscv: add misaligned access testing"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 21.82 seconds
Result: PASS

linux-riscv-bot · 2025-05-14T09:33:34Z

Patch 1: "[v2] selftests: riscv: add misaligned access testing"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 3.75 seconds
Result: ERROR
Output:

WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#45: 
new file mode 100644

WARNING: 'ment' may be misspelled - perhaps 'meant'?
#80: FILE: tools/testing/selftests/riscv/misaligned/common.S:6:
+ *     Clément Léger <cleger@rivosinc.com>
            ^^^^

WARNING: 'ment' may be misspelled - perhaps 'meant'?
#119: FILE: tools/testing/selftests/riscv/misaligned/fpu.S:6:
+ *     Clément Léger <cleger@rivosinc.com>
            ^^^^

WARNING: 'ment' may be misspelled - perhaps 'meant'?
#305: FILE: tools/testing/selftests/riscv/misaligned/gp.S:6:
+ *     Clément Léger <cleger@rivosinc.com>
            ^^^^

WARNING: 'ment' may be misspelled - perhaps 'meant'?
#414: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:6:
+ *     Clément Léger <cleger@rivosinc.com>
            ^^^^

ERROR: Macros with complex values should be enclosed in parentheses
#479: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:71:
+#define fpu_load_proto(__inst, __type) \
+extern __type test_ ## __inst(unsigned long fp_reg, void *addr, unsigned long offset, __type value)

ERROR: Macros with complex values should be enclosed in parentheses
#497: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:89:
+#define gp_load_proto(__inst, __type) \
+extern __type test_ ## __inst(void *addr, unsigned long offset, __type value)

ERROR: Macros with complex values should be enclosed in parentheses
#519: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:111:
+#define TEST_GP_LOAD(__inst, __type_size)					\
+TEST(gp_load_ ## __inst)							\
+{										\
+	int offset, ret;							\
+	uint8_t buf[16] __attribute__((aligned(16)));				\
+										\
+	ret = prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT);			\
+	ASSERT_EQ(ret, 0);							\
+										\
+	for (offset = 1; offset < (__type_size) / 8; offset++) {			\
+		uint ## __type_size ## _t val = VAL ## __type_size;		\
+		uint ## __type_size ## _t *ptr = (uint ## __type_size ## _t *)(buf + offset); \
+		memcpy(ptr, &val, sizeof(val));					\
+		val = test_ ## __inst(ptr, offset, val);			\
+		EXPECT_EQ(VAL ## __type_size, val);				\
+	}									\
+}

WARNING: Prefer __aligned(16) over __attribute__((aligned(16)))
#523: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:115:
+	uint8_t buf[16] __attribute__((aligned(16)));				\

CHECK: spaces preferred around that '*' (ctx:WxV)
#530: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:122:
+		uint ## __type_size ## _t *ptr = (uint ## __type_size ## _t *)(buf + offset); \
 		                          ^

ERROR: Macros with complex values should be enclosed in parentheses
#548: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:140:
+#define TEST_GP_STORE(__inst, __type_size)					\
+TEST(gp_load_ ## __inst)							\
+{										\
+	int offset, ret;							\
+	uint8_t buf[16] __attribute__((aligned(16)));				\
+										\
+	ret = prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT);			\
+	ASSERT_EQ(ret, 0);							\
+										\
+	for (offset = 1; offset < (__type_size) / 8; offset++) {			\
+		uint ## __type_size ## _t val = VAL ## __type_size;		\
+		uint ## __type_size ## _t *ptr = (uint ## __type_size ## _t *)(buf + offset); \
+		memset(ptr, 0, sizeof(val));					\
+		test_ ## __inst(ptr, offset, val);				\
+		memcpy(&val, ptr, sizeof(val));					\
+		EXPECT_EQ(VAL ## __type_size, val);				\
+	}									\
+}

WARNING: Prefer __aligned(16) over __attribute__((aligned(16)))
#552: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:144:
+	uint8_t buf[16] __attribute__((aligned(16)));				\

CHECK: spaces preferred around that '*' (ctx:WxV)
#559: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:151:
+		uint ## __type_size ## _t *ptr = (uint ## __type_size ## _t *)(buf + offset); \
 		                          ^

CHECK: Please use a blank line after function/struct/union/enum declarations
#566: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:158:
+}
+TEST_GP_STORE(sh, 16);

ERROR: Macros with complex values should be enclosed in parentheses
#575: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:167:
+#define __TEST_FPU_LOAD(__type, __inst, __reg_start, __reg_end)			\
+TEST(fpu_load_ ## __inst)							\
+{										\
+	int ret, offset, fp_reg;						\
+	uint8_t buf[16] __attribute__((aligned(16)));				\
+										\
+	ret = prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT);			\
+	ASSERT_EQ(ret, 0);							\
+										\
+	for (fp_reg = __reg_start; fp_reg < __reg_end; fp_reg++) {		\
+		for (offset = 1; offset < 4; offset++) {			\
+			void *load_addr = (buf + offset);			\
+			__type val = VAL_ ## __type ;				\
+										\
+			memcpy(load_addr, &val, sizeof(val));			\
+			val = test_ ## __inst(fp_reg, load_addr, offset, val);	\
+			EXPECT_TRUE(__type ##_equal(val, VAL_## __type));	\
+		}								\
+	}									\
+}

CHECK: Macro argument '__reg_end' may be better as '(__reg_end)' to avoid precedence issues
#575: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:167:
+#define __TEST_FPU_LOAD(__type, __inst, __reg_start, __reg_end)			\
+TEST(fpu_load_ ## __inst)							\
+{										\
+	int ret, offset, fp_reg;						\
+	uint8_t buf[16] __attribute__((aligned(16)));				\
+										\
+	ret = prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT);			\
+	ASSERT_EQ(ret, 0);							\
+										\
+	for (fp_reg = __reg_start; fp_reg < __reg_end; fp_reg++) {		\
+		for (offset = 1; offset < 4; offset++) {			\
+			void *load_addr = (buf + offset);			\
+			__type val = VAL_ ## __type ;				\
+										\
+			memcpy(load_addr, &val, sizeof(val));			\
+			val = test_ ## __inst(fp_reg, load_addr, offset, val);	\
+			EXPECT_TRUE(__type ##_equal(val, VAL_## __type));	\
+		}								\
+	}									\
+}

WARNING: Prefer __aligned(16) over __attribute__((aligned(16)))
#579: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:171:
+	uint8_t buf[16] __attribute__((aligned(16)));				\

CHECK: Please use a blank line after function/struct/union/enum declarations
#595: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:187:
+}
+#define TEST_FPU_LOAD(__type, __inst) \

ERROR: Macros with complex values should be enclosed in parentheses
#607: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:199:
+#define __TEST_FPU_STORE(__type, __inst, __reg_start, __reg_end)		\
+TEST(fpu_store_ ## __inst)							\
+{										\
+	int ret, offset, fp_reg;						\
+	uint8_t buf[16] __attribute__((aligned(16)));				\
+										\
+	ret = prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT);			\
+	ASSERT_EQ(ret, 0);							\
+										\
+	for (fp_reg = __reg_start; fp_reg < __reg_end; fp_reg++) {		\
+		for (offset = 1; offset < 4; offset++) {			\
+										\
+			void *store_addr = (buf + offset);			\
+			__type val = VAL_ ## __type ;				\
+										\
+			test_ ## __inst(fp_reg, store_addr, offset, val);	\
+			memcpy(&val, store_addr, sizeof(val));			\
+			EXPECT_TRUE(__type ## _equal(val, VAL_## __type));	\
+		}								\
+	}									\
+}

CHECK: Macro argument '__reg_end' may be better as '(__reg_end)' to avoid precedence issues
#607: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:199:
+#define __TEST_FPU_STORE(__type, __inst, __reg_start, __reg_end)		\
+TEST(fpu_store_ ## __inst)							\
+{										\
+	int ret, offset, fp_reg;						\
+	uint8_t buf[16] __attribute__((aligned(16)));				\
+										\
+	ret = prctl(PR_SET_UNALIGN, PR_UNALIGN_NOPRINT);			\
+	ASSERT_EQ(ret, 0);							\
+										\
+	for (fp_reg = __reg_start; fp_reg < __reg_end; fp_reg++) {		\
+		for (offset = 1; offset < 4; offset++) {			\
+										\
+			void *store_addr = (buf + offset);			\
+			__type val = VAL_ ## __type ;				\
+										\
+			test_ ## __inst(fp_reg, store_addr, offset, val);	\
+			memcpy(&val, store_addr, sizeof(val));			\
+			EXPECT_TRUE(__type ## _equal(val, VAL_## __type));	\
+		}								\
+	}									\
+}

WARNING: Prefer __aligned(16) over __attribute__((aligned(16)))
#611: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:203:
+	uint8_t buf[16] __attribute__((aligned(16)));				\

CHECK: Please use a blank line after function/struct/union/enum declarations
#628: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:220:
+}
+#define TEST_FPU_STORE(__type, __inst) \

WARNING: Prefer __aligned(16) over __attribute__((aligned(16)))
#643: FILE: tools/testing/selftests/riscv/misaligned/misaligned.c:235:
+	uint8_t buf[16] __attribute__((aligned(16)));

total: 6 errors, 10 warnings, 7 checks, 591 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit f5be6e8e709b ("selftests: riscv: add misaligned access testing") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
CHECK: Macro argument '__reg_end' may be better as '(__reg_end)' to avoid precedence issues
CHECK: Please use a blank line after function/struct/union/enum declarations
CHECK: spaces preferred around that '*' (ctx:WxV)
ERROR: Macros with complex values should be enclosed in parentheses
WARNING: 'ment' may be misspelled - perhaps 'meant'?
WARNING: Prefer __aligned(16) over __attribute__((aligned(16)))
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?

linux-riscv-bot · 2025-05-14T09:34:43Z

Patch 1: "[v2] selftests: riscv: add misaligned access testing"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 67.13 seconds
Result: PASS

linux-riscv-bot · 2025-05-14T09:34:45Z

Patch 1: "[v2] selftests: riscv: add misaligned access testing"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2025-05-14T09:34:47Z

Patch 1: "[v2] selftests: riscv: add misaligned access testing"
kdoc
Desc: Detects for kdoc errors
Duration: 0.83 seconds
Result: PASS

linux-riscv-bot · 2025-05-14T09:34:49Z

Patch 1: "[v2] selftests: riscv: add misaligned access testing"
module-param
Desc: Detect module_param changes
Duration: 0.26 seconds
Result: PASS

linux-riscv-bot · 2025-05-14T09:34:50Z

Patch 1: "[v2] selftests: riscv: add misaligned access testing"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2025-05-14T09:34:52Z

Patch 1: "[v2] selftests: riscv: add misaligned access testing"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.31 seconds
Result: PASS

Linux RISC-V bot and others added 2 commits May 13, 2025 10:51

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linux-riscv-bot force-pushed the workflow__riscv__fixes branch 2 times, most recently from de90874 to 400e3f8 Compare May 14, 2025 13:11

linux-riscv-bot closed this May 22, 2025

linux-riscv-bot deleted the pw962732 branch May 22, 2025 01:04

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[PW_SID:962732] [v2] selftests: riscv: add misaligned access testing#412

[PW_SID:962732] [v2] selftests: riscv: add misaligned access testing#412
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