[PW_SID:963680] riscv: add support for SBI Supervisor Software Events by linux-riscv-bot · Pull Request #422 · linux-riscv/linux

linux-riscv-bot · 2025-05-16T16:27:13Z

PR for series 963680 applied to workflow__riscv__fixes

Name: riscv: add support for SBI Supervisor Software Events
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=963680
Version: 4

Add needed definitions for SBI Supervisor Software Events extension [1]. This extension enables the SBI to inject events into supervisor software much like ARM SDEI. [1] https://lists.riscv.org/g/tech-prs/message/515 Signed-off-by: Clément Léger <cleger@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

The SBI SSE extension allows the supervisor software to be notified by the SBI of specific events that are not maskable. The context switch is handled partially by the firmware which will save registers a6 and a7. When entering kernel we can rely on these 2 registers to setup the stack and save all the registers. Since SSE events can be delivered at any time to the kernel (including during exception handling, we need a way to locate the current_task for context tracking. On RISC-V, it is sotred in scratch when in user space or tp when in kernel space (in which case SSCRATCH is zero). But at a at the beginning of exception handling, SSCRATCH is used to swap tp and check the origin of the exception. If interrupted at that point, then, there is no way to reliably know were is located the current task_struct. Even checking the interruption location won't work as SSE event can be nested on top of each other so the original interruption site might be lost at some point. In order to retrieve it reliably, store the current task in an additionnal __sse_entry_task per_cpu array. This array is then used to retrieve the current task based on the hart ID that is passed to the SSE event handler in a6. That being said, the way the current task struct is stored should probably be reworked to find a better reliable alternative. Since each events (and each CPU for local events) have their own context and can preempt each other, allocate a stack (and a shadow stack if needed for each of them (and for each cpu for local events). When completing the event, if we were coming from kernel with interrupts disabled, simply return there. If coming from userspace or kernel with interrupts enabled, simulate an interrupt exception by setting IE_SIE in CSR_IP to allow delivery of signals to user task. For instance this can happen, when a RAS event has been generated by a user application and a SIGBUS has been sent to a task. Signed-off-by: Clément Léger <cleger@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Add driver level interface to use RISC-V SSE arch support. This interface allows registering SSE handlers, and receive them. This will be used by PMU and GHES driver. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Co-developed-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Signed-off-by: Clément Léger <cleger@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

In order to use SSE within PMU drivers, register a SSE handler for the local PMU event. Reuse the existing overflow IRQ handler and pass appropriate pt_regs. Add a config option RISCV_PMU_SSE to select event delivery via SSE events. Signed-off-by: Clément Léger <cleger@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

linux-riscv-bot · 2025-05-16T16:32:29Z

Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 106.53 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T16:48:58Z

Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 987.60 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T17:10:21Z

Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1280.96 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T17:10:43Z

Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 20.62 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T17:11:06Z

Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 21.65 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T17:11:09Z

Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 1.54 seconds
Result: WARNING
Output:

CHECK: Prefer using the BIT macro
#78: FILE: arch/riscv/include/asm/sbi.h:447:
+#define SBI_SSE_ATTR_CONFIG_ONESHOT	(1 << 0)

CHECK: Prefer using the BIT macro
#80: FILE: arch/riscv/include/asm/sbi.h:449:
+#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SPP	(1 << 0)

CHECK: Prefer using the BIT macro
#81: FILE: arch/riscv/include/asm/sbi.h:450:
+#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SPIE	(1 << 1)

CHECK: Prefer using the BIT macro
#82: FILE: arch/riscv/include/asm/sbi.h:451:
+#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_HSTATUS_SPV	(1 << 2)

CHECK: Prefer using the BIT macro
#83: FILE: arch/riscv/include/asm/sbi.h:452:
+#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_HSTATUS_SPVP	(1 << 3)

CHECK: Prefer using the BIT macro
#94: FILE: arch/riscv/include/asm/sbi.h:463:
+#define SBI_SSE_EVENT_PLATFORM		(1 << 14)

CHECK: Prefer using the BIT macro
#95: FILE: arch/riscv/include/asm/sbi.h:464:
+#define SBI_SSE_EVENT_GLOBAL		(1 << 15)

total: 0 errors, 0 warnings, 7 checks, 89 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit b6a193d93e26 ("riscv: add SBI SSE extension definitions") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 0 warnings, 7 checks, 89 lines checked
CHECK: Prefer using the BIT macro

linux-riscv-bot · 2025-05-16T17:12:17Z

Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 67.03 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T17:12:19Z

Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.24 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T17:12:21Z

Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions"
kdoc
Desc: Detects for kdoc errors
Duration: 0.91 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T17:12:23Z

Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions"
module-param
Desc: Detect module_param changes
Duration: 0.25 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T17:12:25Z

Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.22 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T17:12:27Z

Patch 1: "[v4,1/4] riscv: add SBI SSE extension definitions"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.30 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T17:14:28Z

Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 106.26 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T17:46:30Z

Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 1920.89 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T18:27:08Z

Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 2436.59 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T18:27:30Z

Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 20.52 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T18:27:53Z

Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 21.33 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T18:27:58Z

Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 4.02 seconds
Result: WARNING
Output:

WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#119: 
new file mode 100644

CHECK: Alignment should match open parenthesis
#164: FILE: arch/riscv/include/asm/sse.h:41:
+asmlinkage void do_sse(struct sse_event_arch_data *arch_evt,
+				struct pt_regs *reg);

WARNING: usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc
#250: FILE: arch/riscv/kernel/asm-offsets.c:523:
+	DEFINE(NR_CPUS, NR_CPUS);

CHECK: No space is necessary after a cast
#386: FILE: arch/riscv/kernel/sse.c:128:
+			 (unsigned long) handle_sse, (unsigned long) arch_evt,

total: 0 errors, 2 warnings, 2 checks, 454 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit 0a09f5d86123 ("riscv: add support for SBI Supervisor Software Events extension") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 2 warnings, 2 checks, 454 lines checked
CHECK: Alignment should match open parenthesis
CHECK: No space is necessary after a cast
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
WARNING: usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc

linux-riscv-bot · 2025-05-16T18:29:07Z

Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 67.79 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T18:29:09Z

Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.25 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T18:29:11Z

Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension"
kdoc
Desc: Detects for kdoc errors
Duration: 0.87 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T18:29:13Z

Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension"
module-param
Desc: Detect module_param changes
Duration: 0.27 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T18:29:15Z

Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.22 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T18:29:16Z

Patch 2: "[v4,2/4] riscv: add support for SBI Supervisor Software Events extension"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.31 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T18:31:17Z

Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 105.88 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T18:47:56Z

Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 997.27 seconds
Result: ERROR
Output:

Redirect to /build/tmp.X6LHAo52Cr and /build/tmp.PxnB52Z4L0
Tree base:
0a09f5d861238 ("riscv: add support for SBI Supervisor Software Events extension")
Building the whole tree with the patch
Building the tree before the patch
Building the tree with the patch
New errors added:
--- /build/tmp.F7yXwhUVqO	2025-05-16 18:47:46.729220092 +0000
+++ /build/tmp.rFN4UzdzI1	2025-05-16 18:47:46.732220086 +0000
@@ -117,0 +118 @@
+      1 /build/tmpe9ouq6l9/drivers/firmware/riscv/riscv_sse.c:395:31: warning: variable 'reg_evt' set but not used [-Wunused-but-set-variable]
Per-file breakdown
error/warning file pre:
error/warning file post:
pre: 118 post: 119



real	13m27.406s
user	503m48.835s
sys	98m57.881s

real	1m32.125s
user	3m6.796s
sys	2m11.070s

real	1m28.459s
user	2m49.216s
sys	2m8.484s

linux-riscv-bot · 2025-05-16T19:09:27Z

Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1289.50 seconds
Result: ERROR
Output:

Redirect to /build/tmp.bDcV4iITWI and /build/tmp.lPAid6QjfD
Tree base:
0a09f5d861238 ("riscv: add support for SBI Supervisor Software Events extension")
Building the whole tree with the patch
Building the tree before the patch
Building the tree with the patch
New errors added:
--- /build/tmp.VZJEs99C1a	2025-05-16 19:09:16.741736133 +0000
+++ /build/tmp.SDGvankwIL	2025-05-16 19:09:16.745736126 +0000
@@ -117,0 +118 @@
+      1 /build/tmpe9ouq6l9/drivers/firmware/riscv/riscv_sse.c:395:38: warning: variable 'reg_evt' set but not used [-Wunused-but-set-variable]
Per-file breakdown
error/warning file pre:
pre: 117 post: 118



real	17m52.839s
user	673m54.194s
sys	116m44.101s

real	1m46.868s
user	3m23.876s
sys	2m7.310s

real	1m39.776s
user	2m50.413s
sys	2m1.493s

linux-riscv-bot · 2025-05-16T19:09:50Z

Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 21.03 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:10:13Z

Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 21.55 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:10:18Z

Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 3.87 seconds
Result: WARNING
Output:

WARNING: Co-developed-by and Signed-off-by: name/email do not match
#14: 
Co-developed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Signed-off-by: Clément Léger <cleger@rivosinc.com>

WARNING: 'ment' may be misspelled - perhaps 'meant'?
#55: FILE: MAINTAINERS:20908:
+M:	Clément Léger <cleger@rivosinc.com>
   	    ^^^^

CHECK: Alignment should match open parenthesis
#261: FILE: drivers/firmware/riscv/riscv_sse.c:137:
+	sret = sbi_ecall(SBI_EXT_SSE, SBI_SSE_EVENT_ATTR_READ, evt,
+				     attr_id, 1, phys, 0, 0);

CHECK: Alignment should match open parenthesis
#284: FILE: drivers/firmware/riscv/riscv_sse.c:160:
+	sret = sbi_ecall(SBI_EXT_SSE, SBI_SSE_EVENT_ATTR_WRITE, evt,
+				     attr_id, 1, phys, 0, 0);

CHECK: Blank lines aren't necessary after an open brace '{'
#537: FILE: drivers/firmware/riscv/riscv_sse.c:413:
+				for_each_online_cpu(cpu) {
+

CHECK: Blank lines aren't necessary before a close brace '}'
#538: FILE: drivers/firmware/riscv/riscv_sse.c:414:
+
+				}

CHECK: Blank lines aren't necessary after an open brace '{'
#706: FILE: drivers/firmware/riscv/riscv_sse.c:582:
+			if (!sse_event_is_global(event->evt_id)) {
+

CHECK: Alignment should match open parenthesis
#764: FILE: drivers/firmware/riscv/riscv_sse.c:640:
+static int sse_reboot_notifier(struct notifier_block *nb, unsigned long action,
+				void *data)

CHECK: Please don't use multiple blank lines
#882: FILE: include/linux/riscv_sse.h:56:
+
+

total: 0 errors, 2 warnings, 7 checks, 814 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit 5c9feca65578 ("drivers: firmware: add riscv SSE support") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 2 warnings, 7 checks, 814 lines checked
CHECK: Alignment should match open parenthesis
CHECK: Blank lines aren't necessary after an open brace '{'
CHECK: Blank lines aren't necessary before a close brace '}'
CHECK: Please don't use multiple blank lines
WARNING: 'ment' may be misspelled - perhaps 'meant'?
WARNING: Co-developed-by and Signed-off-by: name/email do not match

linux-riscv-bot · 2025-05-16T19:11:27Z

Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 67.45 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:11:30Z

Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 1.99 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:11:33Z

Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support"
kdoc
Desc: Detects for kdoc errors
Duration: 1.41 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:11:35Z

Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support"
module-param
Desc: Detect module_param changes
Duration: 0.33 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:11:38Z

Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.89 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:11:40Z

Patch 3: "[v4,3/4] drivers: firmware: add riscv SSE support"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.30 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:13:41Z

Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 106.34 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:30:28Z

Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 1006.10 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:52:01Z

Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1290.97 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:52:23Z

Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 20.89 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:52:46Z

Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 21.44 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:52:49Z

Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 2.14 seconds
Result: WARNING
Output:

WARNING: please write a help paragraph that fully describes the config symbol with at least 4 lines
#31: FILE: drivers/perf/Kconfig:108:
+config RISCV_PMU_SSE
+	depends on RISCV_PMU && RISCV_SSE
+	bool "RISC-V PMU SSE events"
+	default n
+	help
+	  Say y if you want to use SSE events to deliver PMU interrupts. This
+	  provides a way to profile the kernel at any level by using NMI-like
+	  SSE events.
+

CHECK: Prefer kernel type 'u32' over 'uint32_t'
#169: FILE: drivers/perf/riscv_pmu_sbi.c:1066:
+static int pmu_sbi_ovf_sse_handler(uint32_t evt, void *arg,

CHECK: Alignment should match open parenthesis
#170: FILE: drivers/perf/riscv_pmu_sbi.c:1067:
+static int pmu_sbi_ovf_sse_handler(uint32_t evt, void *arg,
+	struct pt_regs *regs)

CHECK: Alignment should match open parenthesis
#187: FILE: drivers/perf/riscv_pmu_sbi.c:1084:
+	evt = sse_event_register(SBI_SSE_EVENT_LOCAL_PMU_OVERFLOW, 0,
+				pmu_sbi_ovf_sse_handler, hw_events);

total: 0 errors, 1 warnings, 3 checks, 200 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit 533582005501 ("perf: RISC-V: add support for SSE event") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 1 warnings, 3 checks, 200 lines checked
CHECK: Alignment should match open parenthesis
CHECK: Prefer kernel type 'u32' over 'uint32_t'
WARNING: please write a help paragraph that fully describes the config symbol with at least 4 lines

linux-riscv-bot · 2025-05-16T19:53:58Z

Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 67.34 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:54:00Z

Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.24 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:54:02Z

Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event"
kdoc
Desc: Detects for kdoc errors
Duration: 0.85 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:54:04Z

Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event"
module-param
Desc: Detect module_param changes
Duration: 0.27 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:54:06Z

Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.22 seconds
Result: PASS

linux-riscv-bot · 2025-05-16T19:54:07Z

Patch 4: "[v4,4/4] perf: RISC-V: add support for SSE event"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.29 seconds
Result: PASS

clementleger added 4 commits May 16, 2025 16:27

linux-riscv-bot closed this May 24, 2025

linux-riscv-bot deleted the pw963680 branch May 24, 2025 01:01

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