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1fc0aa9
riscv/kexec_file: Fix comment in purgatory relocator
ziyao233 Mar 26, 2025
ae7f5b8
riscv: Add support for PUD THP
Mar 21, 2025
b0feecf
riscv: save the SR_SUM status over switches
bjdooks-ct Apr 10, 2025
a7205ef
riscv: implement user_access_begin() and families
xhackerustc Apr 10, 2025
ee7ef8a
riscv: uaccess: use input constraints for ptr of __put_user()
xhackerustc Apr 10, 2025
bbf074f
riscv: uaccess: use 'asm goto' for put_user()
xhackerustc Apr 10, 2025
15a7e0c
riscv: uaccess: use 'asm_goto_output' for get_user()
xhackerustc Apr 10, 2025
8046162
riscv: ftrace: support fastcc in Clang for WITH_ARGS
AndybnACT Apr 7, 2025
9f7f40e
riscv: ftrace factor out code defined by !WITH_ARG
AndybnACT Apr 7, 2025
f0f1acb
riscv: ftrace: align patchable functions to 4 Byte boundary
AndybnACT Apr 7, 2025
fede24f
kernel: ftrace: export ftrace_sync_ipi
AndybnACT Apr 7, 2025
6f9f6b5
riscv: ftrace: prepare ftrace for atomic code patching
AndybnACT Apr 7, 2025
5615747
riscv: ftrace: do not use stop_machine to update code
AndybnACT Apr 7, 2025
2b4d1c3
riscv: vector: Support calling schedule() for preemptible Vector
AndybnACT Apr 7, 2025
17a7057
riscv: add a data fence for CMODX in the kernel mode
AndybnACT Apr 7, 2025
9e9ac12
riscv: ftrace: support PREEMPT
AndybnACT Apr 7, 2025
071accf
riscv: Implement HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS
puranjaymohan Apr 7, 2025
1808314
riscv: ftrace: support direct call using call_ops
AndybnACT Apr 7, 2025
66242c2
riscv: Documentation: add a description about dynamic ftrace
AndybnACT Apr 7, 2025
dabfab0
riscv: module: Optimize PLT/GOT entry counting
SiFiveHolland Apr 9, 2025
128006d
RISC-V: Kconfig: Fix help text of CMDLINE_EXTEND
Red54 Mar 28, 2025
52025f5
riscv: kexec_file: Split the loading of kernel and others
Apr 9, 2025
62733b7
riscv: kexec_file: Support loading Image binary file
Apr 9, 2025
0b1fca2
perf symbols: Ignore mapping symbols on riscv
xiaobo55x Apr 9, 2025
8ea28a4
riscv: Make regs_irqs_disabled() more clear
seehearfeel Apr 22, 2025
3cd0abd
riscv: hwprobe: export Zabha extension
Apr 21, 2025
7f51995
riscv: Introduce Zicbop instructions
Apr 21, 2025
c1b24a8
riscv: Add support for Zicbop
Apr 21, 2025
084de85
riscv: Add ARCH_HAS_PREFETCH[W] support with Zicbop
guoren83 Apr 21, 2025
01a9bd9
riscv: xchg: Prefetch the destination word for sc.w
guoren83 Apr 21, 2025
3f92dcd
MAINTAINERS: Update Atish's email address
atishp04 May 5, 2025
08f8ac2
riscv: Improve Kconfig help for RISCV_ISA_V_PREEMPTIVE
mssola May 1, 2025
0054257
riscv: Fix typo EXRACT -> EXTRACT
May 16, 2025
9908f88
riscv: Strengthen duplicate and inconsistent definition of RV_X()
May 16, 2025
4f8d6dc
riscv: Move all duplicate insn parsing macros into asm/insn.h
May 16, 2025
5ae8416
Merge patch series "Move duplicated instructions macros into asm/insn.h"
May 16, 2025
d29656b
riscv: kprobes: Move branch_rs2_idx to insn.h
covanam May 14, 2025
da6de46
riscv: kprobes: Move branch_funct3 to insn.h
covanam May 14, 2025
6d47d90
riscv: kprobes: Remove duplication of RV_EXTRACT_JTYPE_IMM
covanam May 14, 2025
5cefc32
riscv: kprobes: Remove duplication of RV_EXTRACT_RS1_REG
covanam May 14, 2025
a285674
riscv: kprobes: Remove duplication of RV_EXTRACT_BTYPE_IMM
covanam May 14, 2025
c7196c1
riscv: kproves: Remove duplication of RVC_EXTRACT_JTYPE_IMM
covanam May 14, 2025
768007c
riscv: kprobes: Remove duplication of RVC_EXTRACT_C2_RS1_REG
covanam May 14, 2025
f2c715f
riscv: kprobes: Remove duplication of RVC_EXTRACT_BTYPE_IMM
covanam May 14, 2025
284ca2a
riscv: kprobes: Remove duplication of RV_EXTRACT_RD_REG
covanam May 14, 2025
a60c293
riscv: kprobes: Remove duplication of RV_EXTRACT_UTYPE_IMM
covanam May 14, 2025
ee4c45f
riscv: kprobes: Remove duplication of RV_EXTRACT_ITYPE_IMM
covanam May 14, 2025
8d417b3
Merge patch series "riscv: kprobes: Clean up instruction simulation"
May 16, 2025
91d95bd
riscv: Add kprobes KUnit test
covanam May 13, 2025
589039d
riscv: mm: Add support for Svinval extension
mdchitale Jul 2, 2024
d5e77dd
raid6: Add RISC-V SIMD syndrome and recovery calculations
Mar 5, 2025
4ced670
riscv: enable mseal sysmap for RV64
xhackerustc Apr 26, 2025
765c7f7
RISC-V: vDSO: Wire up getrandom() vDSO implementation
xry111 Apr 11, 2025
076d5a8
Adding CI files
May 18, 2025
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Binary file added .github/.MISSING_LINARO_DEP.swp
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Binary file added .github/.swp
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11 changes: 11 additions & 0 deletions .github/MISSING_LINARO_DEP
Original file line number Diff line number Diff line change
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gdb (ltp vma05)
libnuma (ltp vma02-4)
swap file (swapping01)
fusermount (run_fuse_test.sh)
libfuse (run_fuse_test.sh)
mkisofs genisoimage xorrisofs (isofs.sh)
all modules (binfmt_misc0X)
mksquashfs
LTP_TIMEOUT_MUL > 1 (starvation)
libubsan ()
XXX (ltp-aiodio MUST be added)
Binary file added .github/scripts/.patches.sh.swp
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31 changes: 31 additions & 0 deletions .github/scripts/build_ubuntu_defconfig.sh
Original file line number Diff line number Diff line change
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#!/bin/bash
# SPDX-FileCopyrightText: 2024 Rivos Inc.
#
# SPDX-License-Identifier: Apache-2.0

set -euox pipefail
d=$(dirname "${BASH_SOURCE[0]}")
. $d/series/utils.sh

logs=$(get_logs_dir)
f=${logs}/build_ubuntu_defconfig.log

date -Iseconds | tee -a ${f}
echo "Build an ubuntu kernel" | tee -a ${f}
echo "Top 16 commits" | tee -a ${f}
git log -16 --abbrev=12 --pretty="commit %h (\"%s\")" | tee -a ${f}

kernel_base_sha=$(git log -1 --pretty=%H $(git log -1 --reverse --pretty=%H .github)^)
echo "build_name $(git describe --tags ${kernel_base_sha})" | tee -a ${f}
build_name=$(git describe --tags ${kernel_base_sha})

# Build the kernel that will run LTP
export CI_TRIPLE="riscv64-unknown-linux-gnu"
# Use a CFI-enabled toolchain
export PATH=/build/INSTALL_Sept24/bin:$PATH
cp $d/series/kconfigs/ubuntu_defconfig arch/riscv/configs/
$d/series/kernel_builder.sh rv64 testsuites plain gcc | tee -a ${f}

kernel_dir="/build/$(gen_kernel_name rv64 testsuites plain gcc)"
echo $build_name > $kernel_dir/kernel_version
#tar cJvf --exclude $(basename $kernel_path) modules.tar.xz /build/$(gen_kernel_name rv64 testsuites plain gcc)/
2 changes: 2 additions & 0 deletions .github/scripts/ci/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@
from .base import Base, EndTest, Verdict, submit_pw_check
from .shelltest import ShellTest
120 changes: 120 additions & 0 deletions .github/scripts/ci/base.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,120 @@
from abc import ABC, abstractmethod
from enum import Enum
import time
import sys

from libs import utils

sys.path.insert(0, '../libs')
from libs import log_debug

class Verdict(Enum):
PENDING = 0
PASS = 1
FAIL = 2
ERROR = 3
SKIP = 4
WARNING = 5


class EndTest(Exception):
"""
End of Test
"""

class Base(ABC):
"""
Base class for CI Tests.
"""
def __init__(self):
self.start_time = 0
self.end_time = 0
self.verdict = Verdict.PENDING
self.output = ""

def success(self):
self.end_timer()
self.verdict = Verdict.PASS

def error(self, msg):
self.verdict = Verdict.ERROR
self.output = msg
self.end_timer()
raise EndTest

def warning(self, msg):
self.verdict = Verdict.WARNING
self.output = msg
self.end_timer()

def skip(self, msg):
self.verdict = Verdict.SKIP
self.output = msg
self.end_timer()
raise EndTest

def add_failure(self, msg):
self.verdict = Verdict.FAIL
if not self.output:
self.output = msg
else:
self.output += "\n" + msg

def add_failure_end_test(self, msg):
self.add_failure(msg)
self.end_timer()
raise EndTest

def start_timer(self):
self.start_time = time.time()

def end_timer(self):
self.end_time = time.time()

def elapsed(self):
if self.start_time == 0:
return 0
if self.end_time == 0:
self.end_timer()
return self.end_time - self.start_time

def log_err(self, msg):
utils.log_error(f"CI: {self.name}: {msg}")

def log_info(self, msg):
utils.log_info(f"CI: {self.name}: {msg}")

def log_dbg(self, msg):
utils.log_debug(f"CI: {self.name}: {msg}")

@abstractmethod
def run(self, worktree=None):
"""
The child class should implement run() method
If the test fail, it should raise the EndTest exception
"""
pass

@abstractmethod
def post_run(self):
"""
The child class should implement post_run() method
"""
pass


def submit_pw_check(pw, patch, name, verdict, desc, url=None, dry_run=False):

utils.log_debug(f"Submitting the result to PW: dry_run={dry_run}")

if not dry_run:
state = 0

if verdict == Verdict.PASS:
state = 1
if verdict == Verdict.WARNING:
state = 2
if verdict == Verdict.FAIL:
state = 3

pw.post_check(patch, name, state, desc, url)
67 changes: 67 additions & 0 deletions .github/scripts/ci/shelltest.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,67 @@
from gettext import install
import os
import sys

sys.path.insert(0, '../libs')
from libs import RepoTool, cmd_run

from ci import Base, Verdict, EndTest, submit_pw_check

class ShellTest(Base):
"""Run shell test class
This class runs a shell based test
"""

def __init__(self, ci_data, patch, name, desc, sh):

# Common
self.name = name
self.desc = desc
self.ci_data = ci_data

self.sh = sh
self.patch = patch

super().__init__()

self.log_dbg("Initialization completed")

def run(self, worktree=None):

self.log_dbg("Run")
self.start_timer()

current_script_path = os.path.dirname(os.path.abspath(__file__))

cwd = worktree if worktree else self.ci_data.src_dir
cmd = ["bash", f"{current_script_path}/../pw_tests/{self.sh}"]
(ret, stdout, stderr) = cmd_run(cmd, cwd=cwd)

if ret == 0:
submit_pw_check(self.ci_data.pw, self.patch,
self.name, Verdict.PASS,
self.name,
None, self.ci_data.config['dry_run'])
self.success()
elif ret == 250:
url = self.ci_data.gh.create_gist(f"pw{self.ci_data.series['id']}-p{self.patch['id']}",
f"{self.name}-WARNING",
stdout + '\n' + stderr)
submit_pw_check(self.ci_data.pw, self.patch,
self.name, Verdict.WARNING,
self.name,
url, self.ci_data.config['dry_run'])
self.warning(stdout + '\n' + stderr)
else:
url = self.ci_data.gh.create_gist(f"pw{self.ci_data.series['id']}-p{self.patch['id']}",
f"{self.name}-FAIL",
stdout + '\n' + stderr)
submit_pw_check(self.ci_data.pw, self.patch,
self.name, Verdict.FAIL,
self.name,
url, self.ci_data.config['dry_run'])
self.error(stdout + '\n' + stderr)

def post_run(self):

self.log_dbg("Post Run...")
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