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[PW_SID:965782] spi: sophgo: Add SPI NOR controller for SG2042 #440

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[PW_SID:965782] spi: sophgo: Add SPI NOR controller for SG2042 #440

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f4c75ab
dt-bindings: spi: Add bindings for SOPHGO SG2042
sycamoremoon May 23, 2025
9d97f94
mtd: spi-nor: Add GD25LB512ME GigaDevice flash_info
sycamoremoon May 23, 2025
067f892
riscv: dts: sophgo: Add SPI NOR node for SG2042
sycamoremoon May 23, 2025
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6 changes: 5 additions & 1 deletion Documentation/devicetree/bindings/spi/spi-sg2044-nor.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,11 @@ allOf:

properties:
compatible:
const: sophgo,sg2044-spifmc-nor
description: Compatible strings for SOPHGO SPI NOR controller
items:
- enum:
- sophgo,sg2042-spifmc-nor
- const: sophgo,sg2044-spifmc-nor

reg:
maxItems: 1
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18 changes: 18 additions & 0 deletions arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
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Expand Up @@ -68,6 +68,24 @@
status = "okay";
};

&spifmc0 {
status = "okay";

flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
};
};

&spifmc1 {
status = "okay";

flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
};
};

&uart0 {
status = "okay";
};
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24 changes: 24 additions & 0 deletions arch/riscv/boot/dts/sophgo/sg2042.dtsi
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Expand Up @@ -47,6 +47,30 @@
interrupt-parent = <&intc>;
ranges;

spifmc0: spi@7000180000 {
compatible = "sophgo,sg2042-spifmc-nor", "sophgo,sg2044-spifmc-nor";
reg = <0x70 0x00180000 0x0 0x1000000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkgen GATE_CLK_AHB_SF>;
interrupt-parent = <&intc>;
interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstgen RST_SF0>;
status = "disabled";
};

spifmc1: spi@7002180000 {
compatible = "sophgo,sg2042-spifmc-nor", "sophgo,sg2044-spifmc-nor";
reg = <0x70 0x02180000 0x0 0x1000000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkgen GATE_CLK_AHB_SF>;
interrupt-parent = <&intc>;
interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstgen RST_SF1>;
status = "disabled";
};

i2c0: i2c@7030005000 {
compatible = "snps,designware-i2c";
reg = <0x70 0x30005000 0x0 0x1000>;
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17 changes: 17 additions & 0 deletions drivers/mtd/spi-nor/gigadevice.c
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Expand Up @@ -33,6 +33,15 @@ static const struct spi_nor_fixups gd25q256_fixups = {
.post_bfpt = gd25q256_post_bfpt,
};

static void gd25lb512me_default_init(struct spi_nor *nor)
{
nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
}

static const struct spi_nor_fixups gd25lb512me_fixups = {
.default_init = gd25lb512me_default_init,
};

static const struct flash_info gigadevice_nor_parts[] = {
{
.id = SNOR_ID(0xc8, 0x40, 0x15),
Expand Down Expand Up @@ -82,6 +91,14 @@ static const struct flash_info gigadevice_nor_parts[] = {
.size = SZ_16M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
}, {
.id = SNOR_ID(0xc8, 0x67, 0x1a),
.name = "gd25lb512me",
.size = SZ_64M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
.fixups = &gd25lb512me_fixups,
.fixup_flags = SPI_NOR_4B_OPCODES,
},
};

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