[PW_SID:966233] drm: tegra: Fix undefined behavior in left shift operation#444
[PW_SID:966233] drm: tegra: Fix undefined behavior in left shift operation#444linux-riscv-bot wants to merge 1 commit into
Conversation
According to the C11 standard (ISO/IEC 9899:2011, 6.5.7): "If E1 has a signed type and E1 x 2^E2 is not representable in the result type, the behavior is undefined." Shifting 1 << 31 causes signed integer overflow, which leads to undefined behavior. Fix this by explicitly using 'BIT(31)' to ensure the shift operates on an unsigned type, avoiding undefined behavior. Signed-off-by: Yu-Chun Lin <eleanor15x@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
|
Patch 1: "drm: tegra: Fix undefined behavior in left shift operation" |
|
Patch 1: "drm: tegra: Fix undefined behavior in left shift operation" |
|
Patch 1: "drm: tegra: Fix undefined behavior in left shift operation" |
|
Patch 1: "drm: tegra: Fix undefined behavior in left shift operation" |
|
Patch 1: "drm: tegra: Fix undefined behavior in left shift operation" |
|
Patch 1: "drm: tegra: Fix undefined behavior in left shift operation" |
|
Patch 1: "drm: tegra: Fix undefined behavior in left shift operation" |
|
Patch 1: "drm: tegra: Fix undefined behavior in left shift operation" |
|
Patch 1: "drm: tegra: Fix undefined behavior in left shift operation" |
|
Patch 1: "drm: tegra: Fix undefined behavior in left shift operation" |
|
Patch 1: "drm: tegra: Fix undefined behavior in left shift operation" |
|
Patch 1: "drm: tegra: Fix undefined behavior in left shift operation" |
PR for series 966233 applied to workflow__riscv__fixes
Name: drm: tegra: Fix undefined behavior in left shift operation
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=966233
Version: 1