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[PW_SID:967488] riscv: use generic MMIO accessors #455

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[PW_SID:967488] riscv: use generic MMIO accessors #455

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4 changes: 2 additions & 2 deletions arch/riscv/include/asm/io.h
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Original file line number Diff line number Diff line change
Expand Up @@ -68,7 +68,7 @@
ctype *buf = buffer; \
\
do { \
ctype x = __raw_read ## len(addr); \
ctype x = *(const volatile ctype __force *)addr;\
*buf++ = x; \
} while (--count); \
} \
Expand All @@ -85,7 +85,7 @@
const ctype *buf = buffer; \
\
do { \
__raw_write ## len(*buf++, addr); \
*(volatile ctype __force *)addr = *buf++; \
} while (--count); \
} \
afence; \
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65 changes: 0 additions & 65 deletions arch/riscv/include/asm/mmio.h
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Original file line number Diff line number Diff line change
Expand Up @@ -15,71 +15,6 @@
#include <asm/fence.h>
#include <asm/mmiowb.h>

/* Generic IO read/write. These perform native-endian accesses. */
#define __raw_writeb __raw_writeb
static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
{
asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr));
}

#define __raw_writew __raw_writew
static inline void __raw_writew(u16 val, volatile void __iomem *addr)
{
asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr));
}

#define __raw_writel __raw_writel
static inline void __raw_writel(u32 val, volatile void __iomem *addr)
{
asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
}

#ifdef CONFIG_64BIT
#define __raw_writeq __raw_writeq
static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
{
asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr));
}
#endif

#define __raw_readb __raw_readb
static inline u8 __raw_readb(const volatile void __iomem *addr)
{
u8 val;

asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr));
return val;
}

#define __raw_readw __raw_readw
static inline u16 __raw_readw(const volatile void __iomem *addr)
{
u16 val;

asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr));
return val;
}

#define __raw_readl __raw_readl
static inline u32 __raw_readl(const volatile void __iomem *addr)
{
u32 val;

asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
return val;
}

#ifdef CONFIG_64BIT
#define __raw_readq __raw_readq
static inline u64 __raw_readq(const volatile void __iomem *addr)
{
u64 val;

asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr));
return val;
}
#endif

/*
* Unordered I/O memory access primitives. These are even more relaxed than
* the relaxed versions, as they don't even order accesses between successive
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