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400e3f8
Adding CI files
May 14, 2025
90b3110
mm: VM_SHADOW_STACK definition for riscv
deepak0414 Jun 4, 2025
69ba1ae
dt-bindings: riscv: zicfilp and zicfiss in dt-bindings (extensions.yaml)
deepak0414 Jun 4, 2025
585d39b
riscv: zicfiss / zicfilp enumeration
deepak0414 Jun 4, 2025
89f8a5e
riscv: zicfiss / zicfilp extension csr and bit definitions
deepak0414 Jun 4, 2025
3ce29e0
riscv: usercfi state for task and save/restore of CSR_SSP on trap ent…
deepak0414 Jun 4, 2025
0c0bc27
riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE
deepak0414 Jun 4, 2025
eeaf491
riscv/mm: manufacture shadow stack pte
deepak0414 Jun 4, 2025
357087b
riscv/mm: teach pte_mkwrite to manufacture shadow stack PTEs
deepak0414 Jun 4, 2025
5569f8a
riscv/mm: write protect and shadow stack
deepak0414 Jun 4, 2025
6d08228
riscv/mm: Implement map_shadow_stack() syscall
deepak0414 Jun 4, 2025
368b910
riscv/shstk: If needed allocate a new shadow stack on clone
deepak0414 Jun 4, 2025
7e9e5dd
riscv: Implements arch agnostic shadow stack prctls
deepak0414 Jun 4, 2025
a7bc952
prctl: arch-agnostic prctl for indirect branch tracking
deepak0414 Jun 4, 2025
22bfd52
riscv: Implements arch agnostic indirect branch tracking prctls
deepak0414 Jun 4, 2025
bf26512
riscv/traps: Introduce software check exception and uprobe handling
deepak0414 Jun 4, 2025
2bca25d
riscv: signal: abstract header saving for setup_sigcontext
AndybnACT Jun 4, 2025
7ff0475
riscv/signal: save and restore of shadow stack for signal
deepak0414 Jun 4, 2025
95c4cad
riscv/kernel: update __show_regs to print shadow stack register
deepak0414 Jun 4, 2025
132c2b4
riscv/ptrace: riscv cfi status and state via ptrace and in core files
deepak0414 Jun 4, 2025
3493a12
riscv/hwprobe: zicfilp / zicfiss enumeration in hwprobe
deepak0414 Jun 4, 2025
b3e2820
riscv: kernel command line option to opt out of user cfi
deepak0414 Jun 4, 2025
dde7d7e
riscv: enable kernel access to shadow stack memory via FWFT sbi call
deepak0414 Jun 4, 2025
55894ac
arch/riscv: compile vdso with landing pad
cwshu Jun 4, 2025
cdbd65a
riscv: create a config for shadow stack and landing pad instr support
deepak0414 Jun 4, 2025
22d560a
riscv: Documentation for landing pad / indirect branch tracking
deepak0414 Jun 4, 2025
2ffd1e5
riscv: Documentation for shadow stack on riscv
deepak0414 Jun 4, 2025
8ec3d8f
kselftest/riscv: kselftest for user mode cfi
deepak0414 Jun 4, 2025
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29 changes: 29 additions & 0 deletions .github/scripts/build_ubuntu_defconfig.sh
Original file line number Diff line number Diff line change
@@ -0,0 +1,29 @@
#!/bin/bash
# SPDX-FileCopyrightText: 2024 Rivos Inc.
#
# SPDX-License-Identifier: Apache-2.0

set -euox pipefail
d=$(dirname "${BASH_SOURCE[0]}")
. $d/series/utils.sh

logs=$(get_logs_dir)
f=${logs}/build_ubuntu_defconfig.log

date -Iseconds | tee -a ${f}
echo "Build an ubuntu kernel" | tee -a ${f}
echo "Top 16 commits" | tee -a ${f}
git log -16 --abbrev=12 --pretty="commit %h (\"%s\")" | tee -a ${f}

kernel_base_sha=$(git log -1 --pretty=%H $(git log -1 --reverse --pretty=%H .github)^)
echo "build_name $(git describe --tags ${kernel_base_sha})" | tee -a ${f}
build_name=$(git describe --tags ${kernel_base_sha})

# Build the kernel that will run LTP
export CI_TRIPLE="riscv64-linux-gnu"
cp $d/series/kconfigs/ubuntu_defconfig arch/riscv/configs/
$d/series/kernel_builder.sh rv64 testsuites plain gcc | tee -a ${f}

kernel_dir="/build/$(gen_kernel_name rv64 testsuites plain gcc)"
echo $build_name > $kernel_dir/kernel_version
#tar cJvf --exclude $(basename $kernel_path) modules.tar.xz /build/$(gen_kernel_name rv64 testsuites plain gcc)/
2 changes: 2 additions & 0 deletions .github/scripts/ci/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@
from .base import Base, EndTest, Verdict, submit_pw_check
from .shelltest import ShellTest
120 changes: 120 additions & 0 deletions .github/scripts/ci/base.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,120 @@
from abc import ABC, abstractmethod
from enum import Enum
import time
import sys

from libs import utils

sys.path.insert(0, '../libs')
from libs import log_debug

class Verdict(Enum):
PENDING = 0
PASS = 1
FAIL = 2
ERROR = 3
SKIP = 4
WARNING = 5


class EndTest(Exception):
"""
End of Test
"""

class Base(ABC):
"""
Base class for CI Tests.
"""
def __init__(self):
self.start_time = 0
self.end_time = 0
self.verdict = Verdict.PENDING
self.output = ""

def success(self):
self.end_timer()
self.verdict = Verdict.PASS

def error(self, msg):
self.verdict = Verdict.ERROR
self.output = msg
self.end_timer()
raise EndTest

def warning(self, msg):
self.verdict = Verdict.WARNING
self.output = msg
self.end_timer()

def skip(self, msg):
self.verdict = Verdict.SKIP
self.output = msg
self.end_timer()
raise EndTest

def add_failure(self, msg):
self.verdict = Verdict.FAIL
if not self.output:
self.output = msg
else:
self.output += "\n" + msg

def add_failure_end_test(self, msg):
self.add_failure(msg)
self.end_timer()
raise EndTest

def start_timer(self):
self.start_time = time.time()

def end_timer(self):
self.end_time = time.time()

def elapsed(self):
if self.start_time == 0:
return 0
if self.end_time == 0:
self.end_timer()
return self.end_time - self.start_time

def log_err(self, msg):
utils.log_error(f"CI: {self.name}: {msg}")

def log_info(self, msg):
utils.log_info(f"CI: {self.name}: {msg}")

def log_dbg(self, msg):
utils.log_debug(f"CI: {self.name}: {msg}")

@abstractmethod
def run(self, worktree=None):
"""
The child class should implement run() method
If the test fail, it should raise the EndTest exception
"""
pass

@abstractmethod
def post_run(self):
"""
The child class should implement post_run() method
"""
pass


def submit_pw_check(pw, patch, name, verdict, desc, url=None, dry_run=False):

utils.log_debug(f"Submitting the result to PW: dry_run={dry_run}")

if not dry_run:
state = 0

if verdict == Verdict.PASS:
state = 1
if verdict == Verdict.WARNING:
state = 2
if verdict == Verdict.FAIL:
state = 3

pw.post_check(patch, name, state, desc, url)
67 changes: 67 additions & 0 deletions .github/scripts/ci/shelltest.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,67 @@
from gettext import install
import os
import sys

sys.path.insert(0, '../libs')
from libs import RepoTool, cmd_run

from ci import Base, Verdict, EndTest, submit_pw_check

class ShellTest(Base):
"""Run shell test class
This class runs a shell based test
"""

def __init__(self, ci_data, patch, name, desc, sh):

# Common
self.name = name
self.desc = desc
self.ci_data = ci_data

self.sh = sh
self.patch = patch

super().__init__()

self.log_dbg("Initialization completed")

def run(self, worktree=None):

self.log_dbg("Run")
self.start_timer()

current_script_path = os.path.dirname(os.path.abspath(__file__))

cwd = worktree if worktree else self.ci_data.src_dir
cmd = ["bash", f"{current_script_path}/../pw_tests/{self.sh}"]
(ret, stdout, stderr) = cmd_run(cmd, cwd=cwd)

if ret == 0:
submit_pw_check(self.ci_data.pw, self.patch,
self.name, Verdict.PASS,
self.name,
None, self.ci_data.config['dry_run'])
self.success()
elif ret == 250:
url = self.ci_data.gh.create_gist(f"pw{self.ci_data.series['id']}-p{self.patch['id']}",
f"{self.name}-WARNING",
stdout + '\n' + stderr)
submit_pw_check(self.ci_data.pw, self.patch,
self.name, Verdict.WARNING,
self.name,
url, self.ci_data.config['dry_run'])
self.warning(stdout + '\n' + stderr)
else:
url = self.ci_data.gh.create_gist(f"pw{self.ci_data.series['id']}-p{self.patch['id']}",
f"{self.name}-FAIL",
stdout + '\n' + stderr)
submit_pw_check(self.ci_data.pw, self.patch,
self.name, Verdict.FAIL,
self.name,
url, self.ci_data.config['dry_run'])
self.error(stdout + '\n' + stderr)

def post_run(self):

self.log_dbg("Post Run...")
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