[PW_SID:971514] MIPS P8700 variant of the ACLINT IPI controller#520
[PW_SID:971514] MIPS P8700 variant of the ACLINT IPI controller#520linux-riscv-bot wants to merge 7 commits into
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RISC-V APLIC specification defines "hart index" in [1] And similar definitions found for ACLINT in [2] Quote from [1]: Within a given interrupt domain, each of the domain’s harts has a unique index number in the range 0 to 2^14 − 1 (= 16,383). The index number a domain associates with a hart may or may not have any relationship to the unique hart identifier (“hart ID”) that the RISC-V Privileged Architecture assigns to the hart. Two different interrupt domains may employ entirely different index numbers for the same set of harts. Further, [1] says in "4.5 Memory-mapped control region for an interrupt domain": The array of IDC structures may include some for potential hart index numbers that are not actual hart index numbers in the domain. For example, the first IDC structure is always for hart index 0, but 0 is not necessarily a valid index number for any hart in the domain. Support arbitrary hart indices specified in an optional property "riscv,hart-indexes" which is specified as an array of u32 elements, one per interrupt target, listing hart indexes in the same order as in "interrupts-extended". If this property is not specified, fallback to use logical hart indices within the domain. If property not exist, fall back to logical hart indexes Link: https://github.com/riscv/riscv-aia [1] Link: https://github.com/riscvarchive/riscv-aclint [2] Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Use global helper function instead of the local implementation Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add ACLINT-SSWI variant for the MIPS P8700. This CPU has SSWI device compliant with the RISC-V draft spec (see [1]) CPU indexes on this platform are not contiguous, instead it uses bit-fields to encode hart,core,cluster numbers, thus property "riscv,hart-indexes" is mandatory Link: https://github.com/riscvarchive/riscv-aclint [1] Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Refactor Thead specific implementation of the ACLINT-SSWI irqchip. Factor out generic code that serves both Thead and MIPS variants. This generic part is according to the RISC-V draft spec [1]. Link: https://github.com/riscvarchive/riscv-aclint [1] Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Resolve hart index according to assignment in the "riscv,hart-indexes" property as defined in [1] Link: https://github.com/riscvarchive/riscv-aclint [1] Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Move variables to the innermost scope where it is used Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v3,1/7] riscv: helper to parse hart index" |
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Patch 1: "[v3,1/7] riscv: helper to parse hart index" |
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Patch 1: "[v3,1/7] riscv: helper to parse hart index" |
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Patch 1: "[v3,1/7] riscv: helper to parse hart index" |
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Patch 1: "[v3,1/7] riscv: helper to parse hart index" |
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Patch 1: "[v3,1/7] riscv: helper to parse hart index" |
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Patch 1: "[v3,1/7] riscv: helper to parse hart index" |
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Patch 1: "[v3,1/7] riscv: helper to parse hart index" |
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Patch 1: "[v3,1/7] riscv: helper to parse hart index" |
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Patch 1: "[v3,1/7] riscv: helper to parse hart index" |
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Patch 1: "[v3,1/7] riscv: helper to parse hart index" |
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Patch 1: "[v3,1/7] riscv: helper to parse hart index" |
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Patch 2: "[v3,2/7] irqchip/riscv-aplic: use riscv_get_hart_index()" |
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Patch 2: "[v3,2/7] irqchip/riscv-aplic: use riscv_get_hart_index()" |
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Patch 2: "[v3,2/7] irqchip/riscv-aplic: use riscv_get_hart_index()" |
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Patch 2: "[v3,2/7] irqchip/riscv-aplic: use riscv_get_hart_index()" |
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Patch 2: "[v3,2/7] irqchip/riscv-aplic: use riscv_get_hart_index()" |
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Patch 2: "[v3,2/7] irqchip/riscv-aplic: use riscv_get_hart_index()" |
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Patch 2: "[v3,2/7] irqchip/riscv-aplic: use riscv_get_hart_index()" |
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Patch 2: "[v3,2/7] irqchip/riscv-aplic: use riscv_get_hart_index()" |
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Patch 2: "[v3,2/7] irqchip/riscv-aplic: use riscv_get_hart_index()" |
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Patch 2: "[v3,2/7] irqchip/riscv-aplic: use riscv_get_hart_index()" |
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Patch 2: "[v3,2/7] irqchip/riscv-aplic: use riscv_get_hart_index()" |
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Patch 5: "[v3,5/7] irqchip/aslint-sswi: resolve hart index" |
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Patch 5: "[v3,5/7] irqchip/aslint-sswi: resolve hart index" |
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Patch 5: "[v3,5/7] irqchip/aslint-sswi: resolve hart index" |
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Patch 5: "[v3,5/7] irqchip/aslint-sswi: resolve hart index" |
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Patch 6: "[v3,6/7] irqchip/aclint-sswi: reduce data scope" |
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Patch 6: "[v3,6/7] irqchip/aclint-sswi: reduce data scope" |
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Patch 6: "[v3,6/7] irqchip/aclint-sswi: reduce data scope" |
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Patch 6: "[v3,6/7] irqchip/aclint-sswi: reduce data scope" |
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Patch 6: "[v3,6/7] irqchip/aclint-sswi: reduce data scope" |
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Patch 6: "[v3,6/7] irqchip/aclint-sswi: reduce data scope" |
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Patch 6: "[v3,6/7] irqchip/aclint-sswi: reduce data scope" |
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Patch 6: "[v3,6/7] irqchip/aclint-sswi: reduce data scope" |
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Patch 6: "[v3,6/7] irqchip/aclint-sswi: reduce data scope" |
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Patch 6: "[v3,6/7] irqchip/aclint-sswi: reduce data scope" |
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Patch 6: "[v3,6/7] irqchip/aclint-sswi: reduce data scope" |
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Patch 6: "[v3,6/7] irqchip/aclint-sswi: reduce data scope" |
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Patch 7: "[v3,7/7] irqchip/aclint-sswi: remove extra includes" |
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Patch 7: "[v3,7/7] irqchip/aclint-sswi: remove extra includes" |
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Patch 7: "[v3,7/7] irqchip/aclint-sswi: remove extra includes" |
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Patch 7: "[v3,7/7] irqchip/aclint-sswi: remove extra includes" |
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Patch 7: "[v3,7/7] irqchip/aclint-sswi: remove extra includes" |
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Patch 7: "[v3,7/7] irqchip/aclint-sswi: remove extra includes" |
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Patch 7: "[v3,7/7] irqchip/aclint-sswi: remove extra includes" |
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Patch 7: "[v3,7/7] irqchip/aclint-sswi: remove extra includes" |
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Patch 7: "[v3,7/7] irqchip/aclint-sswi: remove extra includes" |
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Patch 7: "[v3,7/7] irqchip/aclint-sswi: remove extra includes" |
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Patch 7: "[v3,7/7] irqchip/aclint-sswi: remove extra includes" |
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Patch 7: "[v3,7/7] irqchip/aclint-sswi: remove extra includes" |
PR for series 971514 applied to workflow__riscv__fixes
Name: MIPS P8700 variant of the ACLINT IPI controller
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=971514
Version: 3