[PW_SID:972501] Basic device tree support for ESWIN EIC7700 RISC-V SoC#538
[PW_SID:972501] Basic device tree support for ESWIN EIC7700 RISC-V SoC#538linux-riscv-bot wants to merge 7 commits into
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Update Documentation for supporting SiFive P550 based CPU Signed-off-by: Darshan Prajapati <darshan.prajapati@einfochips.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Create a config option to build ESWIN SoC specific resources Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add new vendor string to dt bindings. This new vendor string is used by - ESWIN EIC770X SoC - HiFive Premier P550 board which uses EIC7700 SoC. Link: https://www.eswin.com/en/ Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add DT binding documentation for the ESWIN EIC7700 SoC and HiFive Premier P550 Board Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> Reviewed-by: Matthias Brugger <matthias.bgg@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Min Lin <linmin@eswincomputing.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add compatible string for ESWIN EIC7700 PLIC. Signed-off-by: Darshan Prajapati <darshan.prajapati@einfochips.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add initial support for EIC7700 SoC that uses a SiFive Quad-Core P550 CPU cluster. This file is expected to grow as more device drivers are added to the kernel. Signed-off-by: Min Lin <linmin@eswincomputing.com> Co-developed-by: Pritesh Patel <pritesh.patel@einfochips.com> Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com> Co-developed-by: Darshan Prajapati <darshan.prajapati@einfochips.com> Signed-off-by: Darshan Prajapati <darshan.prajapati@einfochips.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add minimal device tree for HiFive Premier P550 Development board Currently the data populated in this DT file is for UART. Signed-off-by: Min Lin <linmin@eswincomputing.com> Co-developed-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v4,1/7] dt-bindings: riscv: Add SiFive P550 CPU compatible" |
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Patch 1: "[v4,1/7] dt-bindings: riscv: Add SiFive P550 CPU compatible" |
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Patch 1: "[v4,1/7] dt-bindings: riscv: Add SiFive P550 CPU compatible" |
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Patch 1: "[v4,1/7] dt-bindings: riscv: Add SiFive P550 CPU compatible" |
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Patch 1: "[v4,1/7] dt-bindings: riscv: Add SiFive P550 CPU compatible" |
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Patch 1: "[v4,1/7] dt-bindings: riscv: Add SiFive P550 CPU compatible" |
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Patch 1: "[v4,1/7] dt-bindings: riscv: Add SiFive P550 CPU compatible" |
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Patch 1: "[v4,1/7] dt-bindings: riscv: Add SiFive P550 CPU compatible" |
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Patch 1: "[v4,1/7] dt-bindings: riscv: Add SiFive P550 CPU compatible" |
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Patch 1: "[v4,1/7] dt-bindings: riscv: Add SiFive P550 CPU compatible" |
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Patch 1: "[v4,1/7] dt-bindings: riscv: Add SiFive P550 CPU compatible" |
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Patch 1: "[v4,1/7] dt-bindings: riscv: Add SiFive P550 CPU compatible" |
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Patch 2: "[v4,2/7] riscv: Add Kconfig option for ESWIN platforms" |
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Patch 2: "[v4,2/7] riscv: Add Kconfig option for ESWIN platforms" |
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Patch 2: "[v4,2/7] riscv: Add Kconfig option for ESWIN platforms" |
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Patch 2: "[v4,2/7] riscv: Add Kconfig option for ESWIN platforms" |
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Patch 2: "[v4,2/7] riscv: Add Kconfig option for ESWIN platforms" |
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Patch 2: "[v4,2/7] riscv: Add Kconfig option for ESWIN platforms" |
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Patch 2: "[v4,2/7] riscv: Add Kconfig option for ESWIN platforms" |
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Patch 2: "[v4,2/7] riscv: Add Kconfig option for ESWIN platforms" |
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Patch 2: "[v4,2/7] riscv: Add Kconfig option for ESWIN platforms" |
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Patch 2: "[v4,2/7] riscv: Add Kconfig option for ESWIN platforms" |
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Patch 2: "[v4,2/7] riscv: Add Kconfig option for ESWIN platforms" |
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Patch 5: "[v4,5/7] dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC" |
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Patch 5: "[v4,5/7] dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC" |
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Patch 5: "[v4,5/7] dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC" |
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Patch 5: "[v4,5/7] dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC" |
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Patch 6: "[v4,6/7] riscv: dts: add initial support for EIC7700 SoC" |
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Patch 6: "[v4,6/7] riscv: dts: add initial support for EIC7700 SoC" |
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Patch 6: "[v4,6/7] riscv: dts: add initial support for EIC7700 SoC" |
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Patch 6: "[v4,6/7] riscv: dts: add initial support for EIC7700 SoC" |
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Patch 6: "[v4,6/7] riscv: dts: add initial support for EIC7700 SoC" |
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Patch 6: "[v4,6/7] riscv: dts: add initial support for EIC7700 SoC" |
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Patch 6: "[v4,6/7] riscv: dts: add initial support for EIC7700 SoC" |
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Patch 6: "[v4,6/7] riscv: dts: add initial support for EIC7700 SoC" |
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Patch 6: "[v4,6/7] riscv: dts: add initial support for EIC7700 SoC" |
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Patch 6: "[v4,6/7] riscv: dts: add initial support for EIC7700 SoC" |
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Patch 6: "[v4,6/7] riscv: dts: add initial support for EIC7700 SoC" |
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Patch 6: "[v4,6/7] riscv: dts: add initial support for EIC7700 SoC" |
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Patch 7: "[v4,7/7] riscv: dts: eswin: add HiFive Premier P550 board device tree" |
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Patch 7: "[v4,7/7] riscv: dts: eswin: add HiFive Premier P550 board device tree" |
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Patch 7: "[v4,7/7] riscv: dts: eswin: add HiFive Premier P550 board device tree" |
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Patch 7: "[v4,7/7] riscv: dts: eswin: add HiFive Premier P550 board device tree" |
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Patch 7: "[v4,7/7] riscv: dts: eswin: add HiFive Premier P550 board device tree" |
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Patch 7: "[v4,7/7] riscv: dts: eswin: add HiFive Premier P550 board device tree" |
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Patch 7: "[v4,7/7] riscv: dts: eswin: add HiFive Premier P550 board device tree" |
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Patch 7: "[v4,7/7] riscv: dts: eswin: add HiFive Premier P550 board device tree" |
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Patch 7: "[v4,7/7] riscv: dts: eswin: add HiFive Premier P550 board device tree" |
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Patch 7: "[v4,7/7] riscv: dts: eswin: add HiFive Premier P550 board device tree" |
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Patch 7: "[v4,7/7] riscv: dts: eswin: add HiFive Premier P550 board device tree" |
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Patch 7: "[v4,7/7] riscv: dts: eswin: add HiFive Premier P550 board device tree" |
PR for series 972501 applied to workflow__riscv__fixes
Name: Basic device tree support for ESWIN EIC7700 RISC-V SoC
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=972501
Version: 4