[PW_SID:976404] RISC-V: avoid using t6/x31 in hand asm#581
[PW_SID:976404] RISC-V: avoid using t6/x31 in hand asm#581linux-riscv-bot wants to merge 2 commits into
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This is technically NFC as nothing functional changes, except for usage of different regs in some of the asm code. This paves the way for using t6 as a global reg for say hoisting percpu base address (with further compiler toggles suh as -ffixed-t6. Lightly tested on QEMU: survives boot/hachbench (thx Atish for the testing). Cc: Yunhui Cui <cuiyunhui@bytedance.com> Cc: Atish Patra <atish.patra@linux.dev> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "RISC-V: avoid using t6/x31 in hand asm" |
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Patch 1: "RISC-V: avoid using t6/x31 in hand asm" |
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Patch 1: "RISC-V: avoid using t6/x31 in hand asm" |
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Patch 1: "RISC-V: avoid using t6/x31 in hand asm" |
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Patch 1: "RISC-V: avoid using t6/x31 in hand asm" |
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Patch 1: "RISC-V: avoid using t6/x31 in hand asm" |
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Patch 1: "RISC-V: avoid using t6/x31 in hand asm" |
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Patch 1: "RISC-V: avoid using t6/x31 in hand asm" |
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Patch 1: "RISC-V: avoid using t6/x31 in hand asm" |
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Patch 1: "RISC-V: avoid using t6/x31 in hand asm" |
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Patch 1: "RISC-V: avoid using t6/x31 in hand asm" |
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Patch 1: "RISC-V: avoid using t6/x31 in hand asm" |
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PR for series 976404 applied to workflow__riscv__fixes
Name: RISC-V: avoid using t6/x31 in hand asm
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=976404
Version: 1