[PW_SID:976535] Support the Cadence MACB/GEM instances on Mobileye EyeQ5 SoCs#584
[PW_SID:976535] Support the Cadence MACB/GEM instances on Mobileye EyeQ5 SoCs#584linux-riscv-bot wants to merge 19 commits into
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Compatibles inside this enum are sorted-ish. Make it sorted. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add cdns,eyeq5-gem as compatible for the integrated GEM block inside Mobileye EyeQ5 SoCs. Add a phandle (and two offset arguments) for accessing syscon registers. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Allow providing tsu_clk without a tx_clk as both are optional. This is about relaxing unneeded constraints. It so happened that in the past HW that needed a tsu_clk always needed a tx_clk. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
On EyeQ5, the GEM DMA controller is coherent with the CPU; allow specifying the information. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Replace all capabilities values by calls to the BIT() macro. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Remove local variables clk_init and init. Those function pointers are always equivalent to macb_config->clk_init and macb_config->init. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Remove NULL checks on macb_config as it is always valid: - either it is its default value &default_gem_config, - or it got overridden using match data. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Introduce macb_dma_is_64b() and macb_dma_is_ptp() helper functions.
Many codepaths are made simpler by dropping conditional compilation.
This implies three changes:
- Always compile related structure definitions inside <macb.h>.
- Make the field hw_dma_cap in struct macb always present.
- MACB_EXT_DESC can be dropped as it is useless now.
The common case is:
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
struct macb_dma_desc_64 *desc_64;
if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
desc_64 = macb_64b_desc(bp, desc);
// ...
}
#endif
And replaced by:
struct macb_dma_desc_64 *desc_64;
if (macb_dma_is_64b(bp)) {
desc_64 = macb_64b_desc(bp, desc);
// ...
}
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Sort #include preprocessor directives. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The MACB driver acts as if TBQPH/RBQPH are configurable on a per queue basis; this is a lie. A single register configures the upper 32 bits of each DMA descriptor buffers for all queues. Concrete actions: - Drop GEM_TBQPH/GEM_RBQPH macros which have a queue index argument. Only use MACB_TBQPH/MACB_RBQPH constants. - Drop struct macb_queue->TBQPH/RBQPH fields. - In macb_init_buffers(): do a single write to TBQPH and RBQPH for all queues instead of a write per queue. - In macb_tx_error_task(): drop the write to TBQPH. - In macb_alloc_consistent(): if allocations give different upper 32-bits, fail. Previously, it would have lead to silent memory corruption as queues would have used the upper 32 bits of the alloc from queue 0 and their own low 32 bits. - In macb_suspend(): if we use the tie off descriptor for suspend, do the write once for all queues instead of once per queue. Fixes: fff8019 ("net: macb: Add 64 bit addressing support for GEM") Fixes: ae1f2a5 ("net: macb: Added support for many RX queues") Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Move from two (Tx/Rx) dma_alloc_coherent() for DMA descriptor rings *per queue* to two dma_alloc_coherent() overall. Issue is with how all queues share the same register for configuring the upper 32-bits of Tx/Rx descriptor rings. For example, with Tx, notice how TBQPH does *not* depend on the queue index: #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2)) #define GEM_TBQPH(hw_q) (0x04C8) queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma)); #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT if (bp->hw_dma_cap & HW_DMA_CAP_64B) queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma)); #endif To maxime our chances of getting valid DMA addresses, we do a single dma_alloc_coherent() across queues. This improves the odds because alloc_pages() guarantees natural alignment. It cannot ensure valid DMA addresses because of IOMMU or codepaths that don't go through alloc_pages(). We error out if all rings don't have the same upper 32 bits, which is better than the current (theoretical, not reproduced) silent corruption caused by hardware that accesses invalid addresses. Two considerations: - dma_alloc_coherent() gives us page alignment. Here we remove this containst meaning each queue's ring won't be page-aligned anymore. - This can save some memory. Less allocations means less overhead (constant cost per alloc) and less wasted bytes due to alignment constraints. Fixes: 02c958d ("net/macb: add TX multiqueue support for gem") Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
If HW is RSC capable, it cannot add dummy bytes at the start of IP packets. Alignment (ie number of dummy bytes) is configured using the RBOF field inside the NCFGR register. On the software side, the skb_reserve(skb, NET_IP_ALIGN) call must only be done if those dummy bytes are added by the hardware; notice the skb_reserve() is done AFTER writing the address to the device. We cannot do the skb_reserve() call BEFORE writing the address because the address field ignores the low 2/3 bits. Conclusion: in some cases, we risk not being able to respect the NET_IP_ALIGN value (which is picked based on unaligned CPU access performance). Fixes: 4df9513 ("net/macb: change RX path for GEM") Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
writel() does a CPU->LE conversion. Drop manual cpu_to_le*() calls.
On little-endian system:
- cpu_to_le32() is a no-op (LE->LE),
- writel() is a no-op (LE->LE),
- dev_addr will therefore not be swapped and written as-is.
On big-endian system:
- cpu_to_le32() is a swap (BE->LE),
- writel() is a swap (BE->LE),
- dev_addr will therefore be swapped twice and written as a BE value.
This was found using sparse:
⟩ make C=2 drivers/net/ethernet/cadence/macb_main.o
warning: incorrect type in assignment (different base types)
expected unsigned int [usertype] bottom
got restricted __le32 [usertype]
warning: incorrect type in assignment (different base types)
expected unsigned short [usertype] top
got restricted __le16 [usertype]
...
Fixes: 89e5785 ("[PATCH] Atmel MACB ethernet driver")
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
LSO is runtime-detected using the PBUF_LSO field inside register designcfg_debug6/GEM_DCFG6. Allow disabling that feature if it is broken by using struct macb_config->caps. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add support for the two GEM instances inside Mobileye EyeQ5 SoCs, using compatible "mobileye,eyeq5-gem". With it, add a custom init sequence that accesses two system-controller registers. Noteworthy: NET_IP_ALIGN=2 on MIPS but the hardware does not align and low bits aren't configurable, so we cannot respect the requested IP header alignment. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Both Cadence GEM Ethernet controllers on EyeQ5 are hardwired through CM3 IO Coherency Units (IOCU). For DMA coherent accesses, BIT(36) must be set in DMA addresses. Implement that in platform-specific dma_map_ops which get attached to both instances of `cdns,eyeq5-gem` through a notifier block. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add both MACB/GEM instances found in the Mobileye EyeQ5 SoC. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The Mobileye EyeQ5 eval board (EPM) embeds two MDIO PHYs. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[net-next,v2,01/18] dt-bindings: net: cdns,macb: sort compatibles" |
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Patch 1: "[net-next,v2,01/18] dt-bindings: net: cdns,macb: sort compatibles" |
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Patch 1: "[net-next,v2,01/18] dt-bindings: net: cdns,macb: sort compatibles" |
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Patch 1: "[net-next,v2,01/18] dt-bindings: net: cdns,macb: sort compatibles" |
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Patch 1: "[net-next,v2,01/18] dt-bindings: net: cdns,macb: sort compatibles" |
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Patch 1: "[net-next,v2,01/18] dt-bindings: net: cdns,macb: sort compatibles" |
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Patch 1: "[net-next,v2,01/18] dt-bindings: net: cdns,macb: sort compatibles" |
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Patch 1: "[net-next,v2,01/18] dt-bindings: net: cdns,macb: sort compatibles" |
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Patch 1: "[net-next,v2,01/18] dt-bindings: net: cdns,macb: sort compatibles" |
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Patch 1: "[net-next,v2,01/18] dt-bindings: net: cdns,macb: sort compatibles" |
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Patch 1: "[net-next,v2,01/18] dt-bindings: net: cdns,macb: sort compatibles" |
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Patch 16: "[net-next,v2,16/18] MIPS: mobileye: add EyeQ5 DMA IOCU support" |
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Patch 16: "[net-next,v2,16/18] MIPS: mobileye: add EyeQ5 DMA IOCU support" |
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Patch 16: "[net-next,v2,16/18] MIPS: mobileye: add EyeQ5 DMA IOCU support" |
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Patch 17: "[net-next,v2,17/18] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers" |
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Patch 17: "[net-next,v2,17/18] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers" |
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Patch 17: "[net-next,v2,17/18] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers" |
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Patch 17: "[net-next,v2,17/18] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers" |
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Patch 17: "[net-next,v2,17/18] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers" |
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Patch 17: "[net-next,v2,17/18] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers" |
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Patch 17: "[net-next,v2,17/18] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers" |
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Patch 17: "[net-next,v2,17/18] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers" |
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Patch 17: "[net-next,v2,17/18] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers" |
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Patch 17: "[net-next,v2,17/18] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers" |
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Patch 17: "[net-next,v2,17/18] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers" |
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Patch 17: "[net-next,v2,17/18] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers" |
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Patch 18: "[net-next,v2,18/18] MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs" |
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Patch 18: "[net-next,v2,18/18] MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs" |
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Patch 18: "[net-next,v2,18/18] MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs" |
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Patch 18: "[net-next,v2,18/18] MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs" |
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Patch 18: "[net-next,v2,18/18] MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs" |
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Patch 18: "[net-next,v2,18/18] MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs" |
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Patch 18: "[net-next,v2,18/18] MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs" |
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Patch 18: "[net-next,v2,18/18] MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs" |
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Patch 18: "[net-next,v2,18/18] MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs" |
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Patch 18: "[net-next,v2,18/18] MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs" |
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Patch 18: "[net-next,v2,18/18] MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs" |
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Patch 18: "[net-next,v2,18/18] MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs" |
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PR for series 976535 applied to workflow__riscv__fixes
Name: Support the Cadence MACB/GEM instances on Mobileye EyeQ5 SoCs
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=976535
Version: 2