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114 changes: 114 additions & 0 deletions Documentation/devicetree/bindings/net/sophgo,cv1800b-dwmac.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/sophgo,cv1800b-dwmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sophgo CV1800B DWMAC glue layer

maintainers:
- Inochi Amaoto <inochiama@gmail.com>

select:
properties:
compatible:
contains:
enum:
- sophgo,cv1800b-dwmac
required:
- compatible

properties:
compatible:
items:
- const: sophgo,cv1800b-dwmac
- const: snps,dwmac-3.70a

reg:
maxItems: 1

clocks:
items:
- description: GMAC main clock
- description: PTP clock

clock-names:
items:
- const: stmmaceth
- const: ptp_ref

interrupts:
maxItems: 1

interrupt-names:
maxItems: 1

resets:
maxItems: 1

reset-names:
const: stmmaceth

required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- interrupt-names
- resets
- reset-names

allOf:
- $ref: snps,dwmac.yaml#

unevaluatedProperties: false

examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>

ethernet@4070000 {
compatible = "sophgo,cv1800b-dwmac", "snps,dwmac-3.70a";
reg = <0x04070000 0x10000>;
clocks = <&clk 35>, <&clk 36>;
clock-names = "stmmaceth", "ptp_ref";
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
phy-handle = <&internal_ephy>;
phy-mode = "internal";
resets = <&rst 12>;
reset-names = "stmmaceth";
rx-fifo-depth = <8192>;
tx-fifo-depth = <8192>;
snps,multicast-filter-bins = <0>;
snps,perfect-filter-entries = <1>;
snps,aal;
snps,txpbl = <8>;
snps,rxpbl = <8>;
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
snps,axi-config = <&gmac0_stmmac_axi_setup>;

mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};

gmac0_mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
queue0 {};
};

gmac0_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
queue0 {};
};

gmac0_stmmac_axi_setup: stmmac-axi-config {
snps,blen = <16 8 4 0 0 0 0>;
snps,rd_osr_lmt = <2>;
snps,wr_osr_lmt = <1>;
};
};
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