feat(b200_core): bump RX FIFO depths from 2K to 4K samples#14
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feat(b200_core): bump RX FIFO depths from 2K to 4K samples#14steve007iii wants to merge 2 commits into
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Override SAMPLE_FIFO_SIZE from default 11 (2048 samples) to 12 (4096) at the b200_core instantiation in libresdr_b210.v. This buffer feeds new_rx_framer and absorbs scheduling jitter between the FPGA radio_clk domain and the USB host. The 2K buffer is shallow enough that ordinary host scheduling jitter causes RX overruns, particularly on Windows where libusb has higher variance than Linux. Observed 6 overruns at 5 MS/s sustained for 5 s on a B210mini over USB 2.0 with the current bin. Resource impact: +133 Kb BRAM per channel (~+5% of XC7A100T total 4860 Kb). Latency worst-case adds +33 us at 61.44 MHz (negligible for typical SDR workflows; non-blocking until FIFO fills). Override applied at integration level; b200_core defaults unchanged. Conservative 2x bump (size 12) chosen over more aggressive 4x (size 13) to keep BRAM footprint minimal. Note: not yet re-validated on hardware after the change by submitter. Plan to follow up with benchmark_rate before/after numbers once Vivado 2024.1 build cycle is completed.
Apply the same depth bump to RADIO_FIFO_SIZE (cross-clock-domain FIFO between radio_clk and bus_clk in radio_legacy.v) for symmetry with the SAMPLE_FIFO_SIZE change in the previous commit. Both FIFOs share the same role: absorbing transient backpressure between adjacent stages of the RX/TX pipeline. RADIO_FIFO_SIZE specifically handles the 150 MHz radio_clk to 200 MHz bus_clk boundary, where async FIFO read/write rate mismatches can accumulate during USB scheduling stalls. Resource impact (cumulative with SAMPLE_FIFO_SIZE bump): - Per RX channel: ~+266 Kb BRAM total (was +133 Kb) - Both channels combined: ~+532 Kb BRAM (vs +266 Kb) - % of XC7A100T BRAM (4860 Kb): ~11% (was ~5.5%) Latency: worst-case +33 us added at 61.44 MS/s (negligible for typical SDR workflows; only relevant when FIFO is fully populated). Override applied at integration level only; b200_core defaults unchanged.
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Summary
Bumps the RX-path FIFO depths in
b200_coreinstantiation from 2K to 4K samples by overriding two parameters at theb200_coreinstantiation inlibresdr_b210.v:SAMPLE_FIFO_SIZEnew_rx_framer(last stage before USB)RADIO_FIFO_SIZEradio_legacy.vBoth FIFOs absorb transient backpressure between adjacent stages of the RX pipeline. Larger depths improve tolerance to host-side scheduling jitter (which causes overruns), particularly under Windows where libusb performance is roughly half of Linux.
Motivation
The current 2048-sample FIFOs are shallow enough that ordinary host scheduling jitter causes RX overruns.
Observed on B210mini (XC7A100T + AD9361) running the current bitstream:
benchmark_rate --rx_rate 5e6 --tx_rate 5e6 --duration 5over USB 2.0Changes
Single file, integration-level only.
b200_core.vdefaults unchanged.No internal module logic touched; no clock-domain, reset, or AXI handshake changes.
Resource impact
XC7A100T BRAM headroom remains comfortable (~78% free).
Why size 12 (4K) and not size 13 (8K)?
Considered both. Size 12 is the conservative choice:
If real-world testing shows residual overruns under heavier load, a follow-up PR could bump to size 13.
Testing status
EXTRA_BUFF_SIZE).benchmark_ratenumbers in a PR comment once compiled.Given the trivial scope of the change and the fact that
b200_corealready exposes both parameters as part of its public interface, opening this PR as-is and committing to follow up with measurements. Happy to mark as Draft if preferred.Compatibility