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1. Direct-Mapped-Cache-Controller Direct-Mapped-Cache-Controller Public

   A parameterized Verilog implementation of a Direct-Mapped Write-Back Write-Allocate Cache Controller with configurable memory latency.

   Verilog

2. RISC-V-Single-Cycle-Processor RISC-V-Single-Cycle-Processor Public

   A 32-bit Single-Cycle RISC-V Processor designed in Verilog HDL and verified using ModelSim.

   Verilog

3. uart-communication-system-verilog uart-communication-system-verilog Public

   UART Communication System in Verilog HDL with TX, RX, loopback integration, and verification testbenches.

   Verilog

4. smart-iot-door-lock-system smart-iot-door-lock-system Public

   IoT based smart door lock system using ESP32-CAM and Telegram for remote monitoring and access control.

   C++