[rtl] Remove redundant halt_if gating in DECODE state

[adsurg]

In the DECODE state of ibex_controller's FSM, halt_if is set in two places when (enter_debug_mode || handle_irq) is true:

1. An outer conditional gated by (stall || id_wb_pending).
2. An inner conditional guarded by (!stall && !special_req && !id_wb_pending) that always sets halt_if = 1 when entering DBG_TAKEN_IF or IRQ_TAKEN.

The outer gating is logically redundant — the inner already sets halt_if = 1 whenever (debug || irq) holds and the FSM transitions through the non-special_req path. In the case the outer is meant to cover (special_req high), the value of halt_if is observationally irrelevant: special_req drives retain_id = 1 (controller.sv:577-581), and id_in_ready_o is computed as

assign id_in_ready_o = ~stall & ~halt_if & ~retain_id;

so retain_id forces id_in_ready_o low independent of halt_if. halt_if has no other consumers (verified: not a module output).

The redundant gating introduced a long combinational arc on the longest topological path:

special_req → !special_req → AND with (stall||id_wb_pending) and
(enter_debug_mode||handle_irq) → halt_if → id_in_ready_o → ctrl_fsm_ns

Consolidating halt_if to its simpler condition removes that arc. The change is pure combinational restructuring (no new register, no pipeline-stage change, no functional difference).

Measurements on a small-config Ibex (RV32IM, RV32MFast, RV32Zca, WB=1, BP=1, no PMP/icache/security) synthesised with Yosys + ltp:

critical_path_gates 119 → 108 (-9.24%)
fmax estimate @ 0.2ns 42.0 → 46.3 MHz (+10.2%)
num_cells (generic) 17,846 → 17,840 (-6)
CoreMark 100i cycles 37,362,985 (unchanged)
CoreMark CRCs 0xe714 / 0x1fd7 / 0x8e3a (golden)
return42 / hello / fwd_test all pass with identical cycle counts

Single block edit; total +13 / -12 lines in ibex_controller.sv.