spi2: Put register to I/O block for the 7-series interface

[occheung]

Ideally, this patch should only involve adding "iob" attributes.

However, IOB inference requires a direct connection from the register to the I/O pad (there are no logic in between).

• The internal sdo reaches the I/O pad directly.
  Requiring users to supply an appropriate sdo keeps it as a direct connection.
• Tristate signals are either shared or derived via a LUT
  Instead of having user to supply a variable length control signals that are identical, it now takes the tristate control signals 1 cycle in prior.

Require migen PR that adds IOB attribute.

[occheung]

The reset_less was removed to make IOB work.

I suspect the way vivado apply IOBs in the same OLOGIC is by naively check if the flip-flops have identical controls.
i.e. resets are the same.

But given the reset is synchronous, it can always be moved into the LUTs prior to the FF. vivado seems to not attempt this transformation for IOB FFs.

One solution is to instruct vivado manually by inserting extract_reset = "yes|no" along with specifying the reset signal itself using direct_reset.

But, do we need the reset_less in the first place?