serial: fixes, more tests and docstrings.#3
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megng1 wants to merge 7 commits intom-labs:serialfrom
megng1:serial
Open
serial: fixes, more tests and docstrings.#3megng1 wants to merge 7 commits intom-labs:serialfrom megng1:serial
megng1 wants to merge 7 commits intom-labs:serialfrom
megng1:serial
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whitequark
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Jan 3, 2020
nmigen_stdio/test/test_serial.py
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| from nmigen.lib.fifo import SyncFIFO | ||
| from nmigen.lib.io import pin_layout | ||
| from nmigen.back.pysim import * | ||
| from nmigen.test.utils import * |
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This module is not called _test because (I think) otherwise test runners would get confused. Nevertheless it is not a part of public API.
added 3 commits
January 3, 2020 10:44
This is a best-effort attempt. The clock divisor signal can still be set to an invalid value during operation.
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