0651-Final-Lab-Project

Final lab project for the EELE 0651 course. Desinging and implementing a single cycle processor.

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
db		db
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
.gitattributes		.gitattributes
README.md		README.md
add2.v		add2.v
alu.v		alu.v
alu.v.bak		alu.v.bak
branchMUX.v		branchMUX.v
controller.v		controller.v
controller.v.bak		controller.v.bak
dataMemory.v		dataMemory.v
dataMemory.v.bak		dataMemory.v.bak
flagMUX.v		flagMUX.v
instructionMemory.v		instructionMemory.v
instructionMemory.v.bak		instructionMemory.v.bak
outPort.v		outPort.v
outPort.v.bak		outPort.v.bak
portMUX.v		portMUX.v
portMux.v.bak		portMux.v.bak
programCounter.v		programCounter.v
programCounter.v.bak		programCounter.v.bak
project.qpf		project.qpf
project.qsf		project.qsf
project.v		project.v
project.v.bak		project.v.bak
projectTest.v		projectTest.v
project_nativelink_simulation.rpt		project_nativelink_simulation.rpt
registerFile.v		registerFile.v
registerFile.v.bak		registerFile.v.bak
subroutineFixed.txt		subroutineFixed.txt
wbMUX.v		wbMUX.v

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