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Apply identifier-length to basic block module and container instance names (fix for #122) #124

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Merged
jpwatt merged 10 commits into from
Apr 30, 2026
Merged

Apply identifier-length to basic block module and container instance names (fix for #122) #124

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f271dfa
Add ClampedSymAttr helper
jpwatt Apr 21, 2026
6f68575
Clamp instance names in more places
jpwatt Apr 22, 2026
21a0291
fix typos
jpwatt Apr 22, 2026
961085f
Declare ClampedSymAttr in header
jpwatt Apr 22, 2026
fd079bc
make ClampStringLength indempotent, return no-op if already clamped
jpwatt Apr 24, 2026
1cb7fb6
clean up un-needed changes
jpwatt Apr 29, 2026
7394c8a
Clean up un-needed changes
jpwatt Apr 29, 2026
fd562b8
Fix inner sym lookups
jpwatt Apr 29, 2026
f32bf50
Clamp concatenated names
jpwatt Apr 29, 2026
665c063
clamp more concatenated strings
jpwatt Apr 30, 2026
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15 changes: 10 additions & 5 deletions compiler/cpp/circt_util.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -366,7 +366,7 @@ mlir::Value GetPathOp(circt::OpBuilder &opb, const ObjectPath &srcPath, const Ob

while (currPath != commonRoot)
{
const mlir::FlatSymbolRefAttr symbolRef = mlir::FlatSymbolRefAttr::get(StringToStringAttr(currPath.back()));
const mlir::FlatSymbolRefAttr symbolRef = mlir::FlatSymbolRefAttr::get(ClampedSymAttr(currPath.back()));

const mlir::Attribute step = circt::kanagawa::PathStepAttr::get(
g_compiler->GetMlirContext(), circt::kanagawa::PathDirection::Parent,
Expand All @@ -384,7 +384,7 @@ mlir::Value GetPathOp(circt::OpBuilder &opb, const ObjectPath &srcPath, const Ob

const std::string stepName = dstPath[currPath.size()];

const mlir::FlatSymbolRefAttr symbolRef = mlir::FlatSymbolRefAttr::get(StringToStringAttr(stepName));
const mlir::FlatSymbolRefAttr symbolRef = mlir::FlatSymbolRefAttr::get(ClampedSymAttr(stepName));

const mlir::Attribute step = circt::kanagawa::PathStepAttr::get(
g_compiler->GetMlirContext(), circt::kanagawa::PathDirection::Child,
Expand Down Expand Up @@ -439,6 +439,11 @@ mlir::StringAttr StringToStringAttr(const std::string &str)
return mlir::StringAttr::get(g_compiler->GetMlirContext(), str);
}

mlir::StringAttr ClampedSymAttr(const std::string &str)
{
return StringToStringAttr(g_compiler->ClampStringLength(str));
}
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mlir::IntegerType GetIntegerType(const size_t width, mlir::IntegerType::SignednessSemantics signedness)
{
return mlir::IntegerType::get(g_compiler->GetMlirContext(), width, signedness);
Expand Down Expand Up @@ -587,7 +592,7 @@ mlir::StringAttr GetFullyQualifiedStringAttr(const ObjectPath &containerPath, co
ObjectPath pathWithField = containerPath;
pathWithField.push_back("__field__" + fieldName);

return StringToStringAttr(FixupStringCirct(SerializePath(pathWithField, '_')));
return ClampedSymAttr(FixupStringCirct(SerializePath(pathWithField, '_')));
}

circt::hw::InnerSymAttr GetFullyQualifiedInnerSymAttr(const ObjectPath &containerPath, const std::string &fieldName)
Expand Down Expand Up @@ -2180,7 +2185,7 @@ mlir::Value ModuleDeclarationHelper::GetPort(circt::OpBuilder &opb, const Object

while (currPath != commonRoot)
{
const mlir::FlatSymbolRefAttr symbolRef = mlir::FlatSymbolRefAttr::get(StringToStringAttr(currPath.back()));
const mlir::FlatSymbolRefAttr symbolRef = mlir::FlatSymbolRefAttr::get(ClampedSymAttr(currPath.back()));

const mlir::Attribute step = circt::kanagawa::PathStepAttr::get(
g_compiler->GetMlirContext(), circt::kanagawa::PathDirection::Parent,
Expand All @@ -2198,7 +2203,7 @@ mlir::Value ModuleDeclarationHelper::GetPort(circt::OpBuilder &opb, const Object

const std::string stepName = dstPath[currPath.size()];

const mlir::FlatSymbolRefAttr symbolRef = mlir::FlatSymbolRefAttr::get(StringToStringAttr(stepName));
const mlir::FlatSymbolRefAttr symbolRef = mlir::FlatSymbolRefAttr::get(ClampedSymAttr(stepName));

const mlir::Attribute step = circt::kanagawa::PathStepAttr::get(
g_compiler->GetMlirContext(), circt::kanagawa::PathDirection::Child,
Expand Down
2 changes: 2 additions & 0 deletions compiler/cpp/circt_util.h
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Original file line number Diff line number Diff line change
Expand Up @@ -69,6 +69,8 @@ mlir::Value LiteralToValue(const Literal& l, circt::OpBuilder& opb, const mlir::

mlir::StringAttr StringToStringAttr(const std::string& str);

mlir::StringAttr ClampedSymAttr(const std::string& str);

size_t GetMlirTypeWidth(const mlir::Type& type);

size_t GetMlirValueWidth(const mlir::Value& v);
Expand Down
30 changes: 18 additions & 12 deletions compiler/cpp/verilog.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -495,7 +495,9 @@ std::string GetRegisterBaseName(const Program &program, const size_t registerInd
return prefix + std::to_string(registerIndex) + "_" + regDesc._name;
}

std::string GetBasicBlockInstanceName(const BasicBlock &basicBlock) { return GetBasicBlockName(basicBlock) + "Impl"; }
std::string GetBasicBlockInstanceName(const BasicBlock &basicBlock) {
return g_compiler->ClampStringLength(GetBasicBlockName(basicBlock) + "Impl");
}

class VerilogCompiler;

Expand Down Expand Up @@ -1641,7 +1643,8 @@ class VerilogCompiler
const mlir::Location location = RegDescToLocation(regDesc);

circt::kanagawa::ContainerInstanceOp::create(opb,
location, circt::hw::InnerSymAttr::get(StringToStringAttr(containerInstancePath.back())),
location,
circt::hw::InnerSymAttr::get(ClampedSymAttr(containerInstancePath.back())),
circt::hw::InnerRefAttr::get(StringToStringAttr(GetCirctDesignName()), leafContainerNameAttr));

// Write clock and reset ports
Expand Down Expand Up @@ -2810,7 +2813,8 @@ class VerilogCompiler
opb.setInsertionPointToEnd(parentContainer.getBodyBlock());

circt::kanagawa::ContainerInstanceOp::create(opb,
location, circt::hw::InnerSymAttr::get(StringToStringAttr(containerInstancePath.back())),
location,
circt::hw::InnerSymAttr::get(ClampedSymAttr(containerInstancePath.back())),
circt::hw::InnerRefAttr::get(StringToStringAttr(GetCirctDesignName()), leafContainerNameAttr));

// Write clock and reset ports
Expand Down Expand Up @@ -5533,7 +5537,7 @@ class VerilogCompiler

str << "global_out_" << regDesc._name << "_" << registerIndex << "_" << writeIndex;

return str.str();
return g_compiler->ClampStringLength(str.str());
}

std::string GetGlobalValidOutName(const size_t registerIndex, const size_t writeIndex) const
Expand All @@ -5542,7 +5546,7 @@ class VerilogCompiler

result += "_valid";

return result;
return g_compiler->ClampStringLength(result);
}

std::string GetGlobalInName(const size_t registerIndex) const
Expand All @@ -5555,7 +5559,7 @@ class VerilogCompiler

str << "global_in_" << regDesc._name << "_" << registerIndex;

return str.str();
return g_compiler->ClampStringLength(str.str());
}

std::string GetGlobalInNextName(const size_t registerIndex) const
Expand All @@ -5568,7 +5572,7 @@ class VerilogCompiler

str << "global_in_" << regDesc._name << "_" << registerIndex << "_next";

return str.str();
return g_compiler->ClampStringLength(str.str());
}

// Returns the name of the variable that holds a global view value
Expand Down Expand Up @@ -5621,7 +5625,7 @@ class VerilogCompiler

ModuleInstanceHelper instance(*this, LocationToCirctLocation(basicBlock._location));

instance.SetModuleName(GetModuleNamePrefix() + GetBasicBlockName(basicBlock));
instance.SetModuleName(g_compiler->ClampStringLength(GetModuleNamePrefix() + GetBasicBlockName(basicBlock)));
instance.SetInstanceName(GetBasicBlockInstanceName(basicBlock));

instance.AddPort("clk", circt::hw::ModulePort::Direction::Input, GetClockType(), "clk");
Expand Down Expand Up @@ -7635,7 +7639,7 @@ class VerilogCompiler
const std::set<size_t> acquiredSemaphores = GetAcquiredSemaphores(basicBlock);
const std::set<size_t> releasedSemaphores = GetReleasedSemaphores(basicBlock);

const std::string fullModuleName = GetModuleNamePrefix() + GetBasicBlockName(basicBlock);
const std::string fullModuleName = g_compiler->ClampStringLength(GetModuleNamePrefix() + GetBasicBlockName(basicBlock));

JsonValue jsonBasicBlock = JsonValue::CreateObject();
JsonValue jsonPorts = JsonValue::CreateArray();
Expand Down Expand Up @@ -11426,7 +11430,7 @@ class VerilogCompiler
basicBlockPorts.push_back(pi._portInfo);
}

const std::string moduleName = GetModuleNamePrefix() + GetBasicBlockName(basicBlock);
const std::string moduleName = g_compiler->ClampStringLength(GetModuleNamePrefix() + GetBasicBlockName(basicBlock));

_compileContext._hwModule =
circt::hw::HWModuleOp::create(opb, mlirBbLocation, opb.getStringAttr(moduleName), basicBlockPorts);
Expand Down Expand Up @@ -11999,7 +12003,8 @@ class VerilogCompiler
opb.setInsertionPointToEnd(parentContainer.getBodyBlock());

circt::kanagawa::ContainerInstanceOp instance = circt::kanagawa::ContainerInstanceOp::create(opb,
GetUnknownLocation(), circt::hw::InnerSymAttr::get(StringToStringAttr(path.back())),
GetUnknownLocation(),
circt::hw::InnerSymAttr::get(ClampedSymAttr(path.back())),
circt::hw::InnerRefAttr::get(StringToStringAttr(GetCirctDesignName()), containerNameAttr));

SafeInsert(_pathToContainerInstance, path, ContainerAndInstance(container, instance));
Expand Down Expand Up @@ -12406,7 +12411,8 @@ void ModuleInstanceHelper::Generate(circt::OpBuilder *const opbIn)
// Use a name hint to ensure the wire generated from this verbatim op
// doesn't conflict with a name of a variable declared in another verbatim op
verbatimOp->setAttr("sv.namehint",
StringToStringAttr(_instanceName + "_" + port.name.str() + "__circt"));
StringToStringAttr(g_compiler->ClampStringLength(
_instanceName + "_" + port.name.str() + "__circt")));

const mlir::Value input =
isClockType ? circt::seq::ToClockOp::create(opb, _location, GetClockType(),
Expand Down
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