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Add --skip-circt-lowering option to emit only CIRCT MLIR#126

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teqdruid merged 2 commits into
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teqdruid/only-circt-asm
May 8, 2026
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Add --skip-circt-lowering option to emit only CIRCT MLIR#126
teqdruid merged 2 commits into
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teqdruid/only-circt-asm

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@teqdruid teqdruid commented May 6, 2026

Adds a new compiler flag that skips the CIRCT lowering passes (which produce SystemVerilog module bodies) and only emits the CIRCT MLIR file. Other Kanagawa-direct outputs (RtlMap.json, _types.sv, etc.) are unaffected. The .sv file is still opened/written by Kanagawa but will not contain any CIRCT-lowered module bodies.

Wires the flag from the Haskell CLI (Options.hs, CmdArgs.hs, FFI.hsc) into the C++ CodeGenOptions struct, gates the CIRCT IR file emission and the call to MlirModule::Generate() in verilog.cpp.

Also adds an add_cli_test() CMake helper for command-line-level tests that invoke the compiler and run verification commands chained via CTest fixtures, plus a first test (test/cli/skip_circt_lowering) that verifies the flag's contract: a .mlir file is produced with CIRCT dialect ops, and no .sv file contains a SystemVerilog module declaration.

Assisted-by: vscode:Claude Opus 4.7

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Pull request overview

This PR adds a new --skip-circt-lowering compiler flag intended to stop the CIRCT lowering/export-to-SystemVerilog path, while still emitting the intermediate CIRCT MLIR for inspection and keeping other Kanagawa outputs intact.

Changes:

  • Adds a new --skip-circt-lowering CLI option and wires it through the Haskell CLI/FFI layer into the C++ CodeGenOptions.
  • Updates Verilog codegen to always emit the CIRCT MLIR when the flag is set, and to skip MlirModule::Generate() (SV export) in that mode.
  • Introduces a test/cli CMake test harness (add_cli_test) plus an initial CLI-level test verifying the flag behavior.

Reviewed changes

Copilot reviewed 11 out of 12 changed files in this pull request and generated 3 comments.

Show a summary per file
File Description
test/CMakeLists.txt Includes the new test/cli subdirectory in the test build.
test/cli/skip_circt_lowering.k Adds a minimal Kanagawa program used by the new CLI test.
test/cli/CMakeLists.txt Adds add_cli_test() helper and registers the skip_circt_lowering CLI test.
test/cli/check_skip_circt_lowering.py Implements verification logic for --skip-circt-lowering outputs.
compiler/hs/app/Options/FFI.hsc Extends the FFI struct pokes to include _skipCirctLowering.
compiler/hs/app/Options/CmdArgs.hs Exposes --skip-circt-lowering in the Haskell CLI options.
compiler/hs/app/Options.hs Adds skip_circt_lowering to the Haskell Compile options record.
compiler/cpp/verilog.cpp Gates CIRCT IR emission and SV generation based on _skipCirctLowering.
compiler/cpp/pch.h Formatting-only changes.
compiler/cpp/options.h Adds _skipCirctLowering to the CodeGenOptions C struct.
compiler/cpp/kanagawa.cpp Formatting-only changes.
build/cmake/test_helper.cmake Removes an extraneous trailing line.
Comments suppressed due to low confidence (1)

compiler/cpp/verilog.cpp:7454

  • The error message hard-codes "circt.mlir", but the actual file path is derived from the output prefix (e.g. ".mlir"). Since this path is now used whenever --skip-circt-lowering is set, it would be more actionable to include the real filename (e.g. _circtAsmFileName) in the exception message.
                std::error_code ec;
                llvm::raw_fd_ostream circtIRFile(_circtAsmFileName, ec);
                if (ec)
                {
                    throw std::runtime_error("Failed to open circt.mlir for writing: " + ec.message());
                }

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Comment thread compiler/hs/app/Options/CmdArgs.hs Outdated
Comment thread compiler/cpp/verilog.cpp Outdated
Comment thread test/cli/check_skip_circt_lowering.py Outdated
Adds a new compiler flag that skips the CIRCT lowering passes (which
produce SystemVerilog module bodies) and only emits the CIRCT MLIR file.
Other Kanagawa-direct outputs (RtlMap.json, _types.sv, etc.) are
unaffected. The .sv file is still opened/written by Kanagawa but will
not contain any CIRCT-lowered module bodies.

Wires the flag from the Haskell CLI (Options.hs, CmdArgs.hs, FFI.hsc)
into the C++ CodeGenOptions struct, gates the CIRCT IR file emission
and the call to MlirModule::Generate() in verilog.cpp.

Also adds an add_cli_test() CMake helper for command-line-level tests
that invoke the compiler and run verification commands chained via
CTest fixtures, plus a first test (test/cli/skip_circt_lowering) that
verifies the flag's contract: a .mlir file is produced with CIRCT
dialect ops, and no .sv file contains a SystemVerilog module
declaration.

Co-authored-by: GitHub Copilot <copilot@github.com>
@teqdruid teqdruid force-pushed the teqdruid/only-circt-asm branch from 4011927 to a8975ac Compare May 6, 2026 19:16
@teqdruid teqdruid marked this pull request as ready for review May 6, 2026 22:15
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teqdruid commented May 6, 2026

For the CMake test stuff: I don't know enough about cmake tests and how they are generally set up to know if this is the "right" way to do this. But I trust that Claude is producing the average of what it was trained on and it looks reasonable to me... at least "cmake reasonable".

Comment thread test/CMakeLists.txt Outdated
@matthew-humphrey
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Does it make more sense to make this a new backend type of mlir?

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teqdruid commented May 8, 2026

Does it make more sense to make this a new backend type of mlir?

This name is likely more accurate WRT the implementation. Kanagawa still produces SV files with it -- just not the stuff that CIRCT produces. Also, an "mlir" or "circt" backend implies (to me) that the whole design is being emitted to the mlir file, but the output relies on the support verilog.

Also -- and this is debatable -- I'm not comfortable calling it "circt" output when there are still soooooo many verbatims. Yeah, it's technically circt IR but really it's got some legacy SV in there.

If we really want to have what I would consider to be a proper circt backend, we should emit everything to mlir files (all of the necessary support systemverilog libraries included) and it should be capable of running through circt's arcsim, which doesn't know anything about verbatims. Transforming the existing systemverilog support libraries on the fly should be pretty trivial given circt's new import verilog functionality. This is all aspirational since I don't have time to make all of this work.

@teqdruid teqdruid merged commit 4678859 into main May 8, 2026
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4 participants