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Merged
teqdruid merged 1 commit into from
May 12, 2026
Merged

Bump CIRCT submodule and adapt to API changes #128

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10 changes: 5 additions & 5 deletions compiler/cpp/circt_util.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -664,7 +664,7 @@ void ConvertOpToCirct(const Operation &op, circt::OpBuilder &opb, const Program
const size_t srcWidth = op._src[0].Width(program);

mlir::Value srcValue = srcToValue(op, 0, op._dst[0].Width(program));
mlir::Value v = circt::comb::createOrFoldNot(opLocation, srcValue, opb, TwoState);
mlir::Value v = circt::comb::createOrFoldNot(opb, opLocation, srcValue, TwoState);

storeDst(op, 0, v);
}
Expand Down Expand Up @@ -954,7 +954,7 @@ mlir::Value AdjustValueWidth(const mlir::Value &srcValue, const size_t desiredWi
{
assert(srcValueWidth > 0);

result = circt::comb::createOrFoldSExt(location, srcValue, opb.getIntegerType(desiredWidth), opb);
result = circt::comb::createOrFoldSExt(opb, location, srcValue, opb.getIntegerType(desiredWidth));
}
else
{
Expand Down Expand Up @@ -2554,12 +2554,12 @@ std::string MlirModule::Generate()
circt::LowerSeqToSVOptions lowerSeqToSVOptions = {};
lowerSeqToSVOptions.lowerToAlwaysFF = !GetCodeGenDeviceConfig()._requirePowerOnReset;
pm.addPass(circt::createLowerSeqToSVPass(lowerSeqToSVOptions));
pm.nest<circt::hw::HWModuleOp>().addPass(circt::sv::createHWCleanupPass()); // this merges always blocks
pm.nest<circt::hw::HWModuleOp>().addPass(circt::sv::createHWCleanup()); // this merges always blocks
pm.addPass(mlir::createCSEPass());
pm.addPass(circt::createSimpleCanonicalizerPass());
pm.nest<circt::hw::HWModuleOp>().addPass(circt::createLowerHWToSVPass());
pm.nest<circt::hw::HWModuleOp>().addPass(circt::sv::createHWLegalizeModulesPass());
pm.nest<circt::hw::HWModuleOp>().addPass(circt::sv::createPrettifyVerilogPass());
pm.nest<circt::hw::HWModuleOp>().addPass(circt::sv::createHWLegalizeModules());
pm.nest<circt::hw::HWModuleOp>().addPass(circt::sv::createPrettifyVerilog());

std::string generatedModule;
llvm::raw_string_ostream generatedModuleStr(generatedModule);
Expand Down
24 changes: 12 additions & 12 deletions compiler/cpp/verilog.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -8312,7 +8312,7 @@ class VerilogCompiler
const std::string instNameIndex = instName + "_" + std::to_string(fifoIndex);

const mlir::Value invFifoStatus =
circt::comb::createOrFoldNot(bbLocation, _compileContext.PortNameToValue(portNameIndex), opb, TwoState);
circt::comb::createOrFoldNot(opb, bbLocation, _compileContext.PortNameToValue(portNameIndex), TwoState);

mlir::Value invFifoStatusSelected;

Expand Down Expand Up @@ -8450,8 +8450,8 @@ class VerilogCompiler
std::ostringstream str;

mlir::Value notSemaphoreFull = circt::comb::createOrFoldNot(
bbLocation,
_compileContext.PortNameToValue("semaphore_full_" + std::to_string(semaphoreIndex) + "_in"), opb,
opb, bbLocation,
_compileContext.PortNameToValue("semaphore_full_" + std::to_string(semaphoreIndex) + "_in"),
TwoState);

allowThreadPredicates.push_back(notSemaphoreFull);
Expand Down Expand Up @@ -8571,7 +8571,7 @@ class VerilogCompiler

// Don't trust fifo control signals during the reset sequence
allowThreadTerms.push_back(
circt::comb::createOrFoldNot(bbLocation, _compileContext.PortNameToValue("rst"), opb, TwoState));
circt::comb::createOrFoldNot(opb, bbLocation, _compileContext.PortNameToValue("rst"), TwoState));

if (!checkControlFifo0Only)
{
Expand Down Expand Up @@ -8650,7 +8650,7 @@ class VerilogCompiler
std::ostringstream str;

writeConditions.push_back(circt::comb::createOrFoldNot(
bbLocation, _compileContext.PortNameToValue("input_fifo_empty_" + std::to_string(i)), opb,
opb, bbLocation, _compileContext.PortNameToValue("input_fifo_empty_" + std::to_string(i)),
TwoState));

if ((i == 0) && checkControlFifo0Only)
Expand Down Expand Up @@ -8762,7 +8762,7 @@ class VerilogCompiler
mlir::SmallVector<mlir::Value> initialCallMadeThisCycleInputs;

initialCallMadeThisCycleInputs.push_back(
circt::comb::createOrFoldNot(bbLocation, initialCallMadeRegBackedge, opb, TwoState));
circt::comb::createOrFoldNot(opb, bbLocation, initialCallMadeRegBackedge, TwoState));
initialCallMadeThisCycleInputs.push_back(allowNewThread);
initialCallMadeThisCycleInputs.push_back(_compileContext.PortNameToValue("allow_initial_call_in"));

Expand All @@ -8788,7 +8788,7 @@ class VerilogCompiler
if (basicBlock._inputFifoCount > 0)
{
const mlir::Value inputFifoNotEmpty = circt::comb::createOrFoldNot(
bbLocation, _compileContext.PortNameToValue("input_fifo_empty_0"), opb, TwoState);
opb, bbLocation, _compileContext.PortNameToValue("input_fifo_empty_0"), TwoState);

const mlir::Value fifoNotEmptyAllowNewThread =
circt::comb::AndOp::create(opb, bbLocation, inputFifoNotEmpty, allowNewThread, TwoState);
Expand All @@ -8797,7 +8797,7 @@ class VerilogCompiler
bbLocation, fifoNotEmptyAllowNewThread, initialCallMadeThisCycle, TwoState);

const mlir::Value initCallNotThisCycle =
circt::comb::createOrFoldNot(bbLocation, initialCallMadeThisCycle, opb, TwoState);
circt::comb::createOrFoldNot(opb, bbLocation, initialCallMadeThisCycle, TwoState);

const mlir::Value inputFifoRden0 =
circt::comb::AndOp::create(opb, bbLocation, stageValid0, initCallNotThisCycle, TwoState);
Expand Down Expand Up @@ -8853,7 +8853,7 @@ class VerilogCompiler
else
{
const mlir::Value inputFifoNotEmpty = circt::comb::createOrFoldNot(
bbLocation, _compileContext.PortNameToValue("input_fifo_empty_0"), opb, TwoState);
opb, bbLocation, _compileContext.PortNameToValue("input_fifo_empty_0"), TwoState);

result._startNewThread =
circt::comb::AndOp::create(opb, bbLocation, allowNewThread, inputFifoNotEmpty, TwoState);
Expand All @@ -8872,7 +8872,7 @@ class VerilogCompiler
{
// Inverted because a value of "0" in controlStateRecords means that everything is OK
const mlir::Value noUnderflow = circt::comb::createOrFoldNot(
bbLocation, _compileContext.PortNameToValue("input_fifo_underflow_" + std::to_string(i)), opb,
opb, bbLocation, _compileContext.PortNameToValue("input_fifo_underflow_" + std::to_string(i)),
TwoState);

controlStateRecords[ControlStateBit::InputFifoUnderflow].push_back(noUnderflow);
Expand Down Expand Up @@ -8906,7 +8906,7 @@ class VerilogCompiler
const mlir::Value reduced = circt::comb::AndOp::create(opb, bbLocation, expressions, TwoState);

// Flip bits so that 0 means everything is OK, 1 means something is causing a slow down
controlStateBits[bitIndex] = circt::comb::createOrFoldNot(bbLocation, reduced, opb, TwoState);
controlStateBits[bitIndex] = circt::comb::createOrFoldNot(opb, bbLocation, reduced, TwoState);
}

// Reverse control state bits because concat op expects most significant bit first
Expand Down Expand Up @@ -12041,7 +12041,7 @@ class VerilogCompiler

if (reversePredicateMeaning)
{
predicate = circt::comb::createOrFoldNot(opLocation, predicate, opb, TwoState);
predicate = circt::comb::createOrFoldNot(opb, opLocation, predicate, TwoState);
}

result = circt::comb::AndOp::create(opb, opLocation, enable, predicate, TwoState);
Expand Down
2 changes: 1 addition & 1 deletion thirdparty/circt
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Submodule circt updated 914 files
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