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Msus onboard 12 to8bit#195

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hsemwal wants to merge 182 commits into
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MSUS_onboard_12_to8bit
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Msus onboard 12 to8bit#195
hsemwal wants to merge 182 commits into
mainfrom
MSUS_onboard_12_to8bit

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@hsemwal
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@hsemwal hsemwal commented May 17, 2026

I unplugged the USB and power overnight, and all of sudden, when I attempt to run the FPGA, I get the following error:

Process _fpga_recv:
Traceback (most recent call last):
File "..\Lib\multiprocessing\process.py", line 313, in _bootstrap
self.run()
~~~~~~~~^^
File "..\multiprocessing\process.py", line 108, in run
self._target(*self._args, **self._kwargs)
~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "..\mio\mio\stream_daq.py", line 265, in _fpga_recv
dev = self._init_okdev(BIT_FILE, read_length)
File "..\mio\mio\stream_daq.py", line 207, in _init_okdev
dev.set_wire(0x00, 0b0010)
~~~~~~~~~~~~^^^^^^^^^^^^^^
File "..\mio\mio\devices\opalkelly.py", line 102, in set_wire
raise DeviceConfigurationError(f"Wire update failed: {ret}")
mio.exceptions.DeviceConfigurationError: Wire update failed: -15

What did I do??


📚 Documentation preview 📚: https://miniscope-io--195.org.readthedocs.build/en/195/

hsemwal and others added 30 commits December 3, 2024 14:04
- trying to change the config file to match the firmware
- generalize the config file and stream_daq.py
- Investigating where buffer per frame value is getting set at 3, likely self._buffer_npix is getting its values
- adjusting the StreamBit header file and the config file according to
- implemented on VS code
- modified pixel value depth to 8 bits instead of 10
- csv not outputting correct frame (frame number increasing on oscilloscope, but not on the csv counter through MIO)
- changing yml file
- added MSUS config file
and changed baud rate to 5 MHz for FPGA
…number of buffers and dummy words to better match the firmware)
- changing the settings on the config and stream.py files, still not getting any images
- only 3 data buffers, possibly error is coming from here
- added MSUS config file
and changed baud rate to 5 MHz for FPGA
…number of buffers and dummy words to better match the firmware)
- changing the settings on the config and stream.py files, still not getting any images
- only 3 data buffers, possibly error is coming from here
Copied last function in types.py and copied to my code (maybe accidentally changed)
Changed yml MSUS file bitstream pointer to 5 MHz
Changed blocksize back to 4000, which should include the data+header
For some reason MSUS config had an incorrectly tabbed if statement, hopefully fixed in this commit
Output data that the FPGA receives (so far, just \x00\x8f\xff)
right now the data is not properly being read by MIO and the output text file gives some 0x00....0x8f....0xff which is not what is being sent out from the dev board
sneakers-the-rat and others added 28 commits August 1, 2025 20:03
msus - test frame processing values with bright/dark sample
Converting datastream to 8bit value. Will need to modularize this a bit better, currently inside of buffer_to_array
Increased time for debug and comments
Increased time for debug and comments
Just modified some comments and added a test as a proof of concept
We now have video recording capabilities on MIO
minor update to mio before starting branch to fix 12 MHz version
Implemented ROI row by row flexibility
Implementing ROI based MSUS/MIO interface (changed to 8 MHz)
Branch for 12 to 8 bit conversion that is already processed on board the MSUS
Corrected yaml file for new data block sizes
Created an MSUS ROI Yaml file for testing
testing for ROI from MSUS
changes to MSUS ROI for the smaller region of interest MSUS ROI (8 MHz output, 120x120x8 pixel)
@sneakers-the-rat
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seems like some kind of i/o error with the opalkelly board. seems like more of an issue than a pull request?

@hsemwal hsemwal closed this May 18, 2026
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