VHDLMachines

A package for defining the .machine format for VHDL Logic-Labelled Finite-State Machines.

Name		Name	Last commit message	Last commit date
Latest commit History 688 Commits
.github/workflows		.github/workflows
Sources/VHDLMachines		Sources/VHDLMachines
Tests		Tests
.gitignore		.gitignore
.swiftformat.json		.swiftformat.json
.swiftlint.yml		.swiftlint.yml
CITATION.cff		CITATION.cff
Package.swift		Package.swift
README.md		README.md

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